ppc32_exec.c

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   m_uint16_t imm = bits(insn,0,15);
   m_uint32_t vaddr;

   vaddr = sign_extend_32(imm,16);
   
   if (ra != 0)
      vaddr += cpu->gpr[ra];

   ppc32_exec_memop(cpu,PPC_MEMOP_LWZ,vaddr,rd);
   return(0);
}

/* LWZU - Load Word and Zero with Update */
static fastcall int ppc32_exec_LWZU(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   m_uint16_t imm = bits(insn,0,15);
   m_uint32_t vaddr;

   vaddr = cpu->gpr[ra] + sign_extend_32(imm,16);
   ppc32_exec_memop(cpu,PPC_MEMOP_LWZ,vaddr,rd);
   cpu->gpr[ra] = vaddr;
   return(0);
}

/* LWZUX - Load Word and Zero with Update Indexed */
static fastcall int ppc32_exec_LWZUX(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint32_t vaddr;

   vaddr = cpu->gpr[ra] + cpu->gpr[rb];
   ppc32_exec_memop(cpu,PPC_MEMOP_LWZ,vaddr,rd);
   cpu->gpr[ra] = vaddr;
   return(0);
}

/* LWZX - Load Word and Zero Indexed */
static fastcall int ppc32_exec_LWZX(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint32_t vaddr;

   vaddr = cpu->gpr[rb];

   if (ra != 0)
      vaddr += cpu->gpr[ra];

   ppc32_exec_memop(cpu,PPC_MEMOP_LWZ,vaddr,rd);
   return(0);
}

/* LWARX - Load Word and Reserve Indexed */
static fastcall int ppc32_exec_LWARX(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint32_t vaddr;

   vaddr = cpu->gpr[rb];

   if (ra != 0)
      vaddr += cpu->gpr[ra];

   cpu->reserve = 1;
   ppc32_exec_memop(cpu,PPC_MEMOP_LWZ,vaddr,rd);
   return(0);
}

/* LFD - Load Floating-Point Double */
static fastcall int ppc32_exec_LFD(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   m_uint16_t imm = bits(insn,0,15);
   m_uint32_t vaddr;

   vaddr = sign_extend_32(imm,16);
   
   if (ra != 0)
      vaddr += cpu->gpr[ra];

   ppc32_exec_memop(cpu,PPC_MEMOP_LFD,vaddr,rd);
   return(0);
}

/* LFDU - Load Floating-Point Double with Update */
static fastcall int ppc32_exec_LFDU(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   m_uint16_t imm = bits(insn,0,15);
   m_uint32_t vaddr;

   vaddr = cpu->gpr[ra] + sign_extend_32(imm,16);
   ppc32_exec_memop(cpu,PPC_MEMOP_LFD,vaddr,rd);
   cpu->gpr[ra] = vaddr;
   return(0);
}

/* LFDUX - Load Floating-Point Double with Update Indexed */
static fastcall int ppc32_exec_LFDUX(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint32_t vaddr;

   vaddr = cpu->gpr[ra] + cpu->gpr[rb];
   ppc32_exec_memop(cpu,PPC_MEMOP_LFD,vaddr,rd);
   cpu->gpr[ra] = vaddr;
   return(0);
}

/* LFDX - Load Floating-Point Double Indexed */
static fastcall int ppc32_exec_LFDX(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint32_t vaddr;

   vaddr = cpu->gpr[rb];

   if (ra != 0)
      vaddr += cpu->gpr[ra];

   ppc32_exec_memop(cpu,PPC_MEMOP_LFD,vaddr,rd);
   return(0);
}

/* LSWI - Load String Word Immediate */
static fastcall int ppc32_exec_LSWI(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int nb = bits(insn,11,15);
   m_uint32_t vaddr = 0;
   int r;

   if (ra != 0)
      vaddr += cpu->gpr[ra];

   if (nb == 0)
      nb = 32;

   r = rd - 1;
   cpu->sw_pos = 0;

   while(nb > 0) {
      if (cpu->sw_pos == 0) {
         r = (r + 1) & 0x1F;
         cpu->gpr[r] = 0;
      }
      
      ppc32_exec_memop(cpu,PPC_MEMOP_LSW,vaddr,r);
      cpu->sw_pos += 8;

      if (cpu->sw_pos == 32)
         cpu->sw_pos = 0; 

      vaddr++;
      nb--;
   }

   return(0);
}

/* LSWX - Load String Word Indexed */
static fastcall int ppc32_exec_LSWX(cpu_ppc_t *cpu,ppc_insn_t insn)
{  
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint32_t vaddr;
   int r,nb;

   vaddr = cpu->gpr[rb];

   if (ra != 0)
      vaddr += cpu->gpr[ra];

   nb = cpu->xer & PPC32_XER_BC_MASK;
   r = rd - 1;
   cpu->sw_pos = 0;

   while(nb > 0) {
      if (cpu->sw_pos == 0) {
         r = (r + 1) & 0x1F;
         cpu->gpr[r] = 0;
      }
      
      ppc32_exec_memop(cpu,PPC_MEMOP_LSW,vaddr,r);
      cpu->sw_pos += 8;

      if (cpu->sw_pos == 32)
         cpu->sw_pos = 0; 

      vaddr++;
      nb--;
   }

   return(0);
}

/* MCRF - Move Condition Register Field */
static fastcall int ppc32_exec_MCRF(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,23,25);
   int rs = bits(insn,18,20);

   cpu->cr_fields[rd] = cpu->cr_fields[rs];
   return(0);
}

/* MFCR - Move from Condition Register */
static fastcall int ppc32_exec_MFCR(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);

   cpu->gpr[rd] = ppc32_get_cr(cpu);
   return(0);
}

/* MFMSR - Move from Machine State Register */
static fastcall int ppc32_exec_MFMSR(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);

   cpu->gpr[rd] = cpu->msr;
   return(0);
}

/* MFTBU - Move from Time Base (Up) */
static fastcall int ppc32_exec_MFTBU(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);

   cpu->gpr[rd] = cpu->tb >> 32;
   return(0);
}

/* MFTBL - Move from Time Base (Lo) */
static fastcall int ppc32_exec_MFTBL(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);

   cpu->tb += 50;

   cpu->gpr[rd] = cpu->tb & 0xFFFFFFFF;
   return(0);
}

/* MFSPR - Move from Special-Purpose Register */
static fastcall int ppc32_exec_MFSPR(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd   = bits(insn,21,25);
   int spr0 = bits(insn,16,20);
   int spr1 = bits(insn,11,15);
   u_int spr;
   
   spr = (spr1 << 5) | spr0;
   cpu->gpr[rd] = 0;
   
   //cpu_log(cpu->gen,"SPR","reading SPR=%d at cpu->ia=0x%8.8x\n",spr,cpu->ia);

   if ((spr1 == 0x10) || (spr1 == 0x11)) {
      cpu->gpr[rd] = ppc32_get_bat_spr(cpu,spr);
      return(0);
   }

   switch(spr) {
      case PPC32_SPR_XER:
         cpu->gpr[rd] = cpu->xer | (cpu->xer_ca << PPC32_XER_CA_BIT);
         break;
      case PPC32_SPR_DSISR:
         cpu->gpr[rd] = cpu->dsisr;
         break;
      case PPC32_SPR_DAR:
         cpu->gpr[rd] = cpu->dar;
         break;
      case PPC32_SPR_DEC:
         cpu->gpr[rd] = cpu->dec;
         break;
      case PPC32_SPR_SDR1:
         cpu->gpr[rd] = cpu->sdr1;
         break;
      case PPC32_SPR_SRR0:
         cpu->gpr[rd] = cpu->srr0;
         break;
      case PPC32_SPR_SRR1:
         cpu->gpr[rd] = cpu->srr1;
         break;
      case PPC32_SPR_TBL_READ:
         cpu->gpr[rd] = cpu->tb & 0xFFFFFFFF;
         break;
      case PPC32_SPR_TBU_READ:
         cpu->gpr[rd] = cpu->tb >> 32;
         break;
      case PPC32_SPR_SPRG0:
         cpu->gpr[rd] = cpu->sprg[0];
         break;
      case PPC32_SPR_SPRG1:
         cpu->gpr[rd] = cpu->sprg[1];
         break;
      case PPC32_SPR_SPRG2:
         cpu->gpr[rd] = cpu->sprg[2];
         break;
      case PPC32_SPR_SPRG3:
         cpu->gpr[rd] = cpu->sprg[3];
         break;
      case PPC32_SPR_PVR:
         cpu->gpr[rd] = cpu->pvr;
         break;
      case PPC32_SPR_HID0:
         cpu->gpr[rd] = cpu->hid0;
         break;
      case PPC32_SPR_HID1:
         cpu->gpr[rd] = cpu->hid1;
         break;
      case PPC405_SPR_PID:
         cpu->gpr[rd] = cpu->ppc405_pid;
         break;

      /* MPC860 IMMR */
      case 638:
         cpu->gpr[rd] = cpu->mpc860_immr;
         break;

      default:
         cpu->gpr[rd] = 0x0;
         //printf("READING SPR = %d\n",spr);
   }

   return(0);
}

/* MFSR - Move From Segment Register */
static fastcall int ppc32_exec_MFSR(cpu_ppc_t *cpu,ppc_insn_t insn)
{   
   int rd = bits(insn,21,25);
   int sr = bits(insn,16,19);

   cpu->gpr[rd] = cpu->sr[sr];
   return(0);
}

/* MFSRIN - Move From Segment Register Indirect */
static fastcall int ppc32_exec_MFSRIN(cpu_ppc_t *cpu,ppc_insn_t insn)
{   
   int rd = bits(insn,21,25);
   int rb = bits(insn,11,15);

   cpu->gpr[rd] = cpu->sr[cpu->gpr[rb] >> 28];
   return(0);
}

/* MTCRF - Move to Condition Register Fields */
static fastcall int ppc32_exec_MTCRF(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rs = bits(insn,21,25);
   int crm = bits(insn,12,19);
   int i;
   
   for(i=0;i<8;i++)
      if (crm & (1 << (7 - i)))
         cpu->cr_fields[i] = (cpu->gpr[rs] >> (28 - (i << 2))) & 0x0F;

   return(0);
}

/* MTMSR - Move to Machine State Register */
static fastcall int ppc32_exec_MTMSR(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rs = bits(insn,21,25);

   cpu->msr = cpu->gpr[rs];
   cpu->irq_check = (cpu->msr & PPC32_MSR_EE) && cpu->irq_pending;

   //printf("New MSR = 0x%8.8x at cpu->ia=0x%8.8x\n",cpu->msr,cpu->ia);
   return(0);
}

/* MTSPR - Move to Special-Purpose Register */
static fastcall int ppc32_exec_MTSPR(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd   = bits(insn,21,25);
   int spr0 = bits(insn,16,20);
   int spr1 = bits(insn,11,15);
   u_int spr;
   
   spr = (spr1 << 5) | spr0;

   //cpu_log(cpu->gen,"SPR","writing SPR=%d, val=0x%8.8x at cpu->ia=0x%8.8x\n",
   //        spr,cpu->ia,cpu->gpr[rd]);

   if ((spr1 == 0x10) || (spr1 == 0x11)) {
      ppc32_set_bat_spr(cpu,spr,cpu->gpr[rd]);
      return(0);
   }

   switch(spr) {
      case PPC32_SPR_XER:
         cpu->xer = cpu->gpr[rd] & ~PPC32_XER_CA;
         cpu->xer_ca = (cpu->gpr[rd] >> PPC32_XER_CA_BIT) & 0x1;
         break;
      case PPC32_SPR_DEC:
         //printf("WRITING DECR 0x%8.8x AT IA=0x%8.8x\n",cpu->gpr[rd],cpu->ia);
         cpu->dec = cpu->gpr[rd];
         cpu->timer_irq_armed = TRUE;
         break;
      case PPC32_SPR_SDR1:
         cpu->sdr1 = cpu->gpr[rd];
         ppc32_mem_invalidate_cache(cpu);
         break;
      case PPC32_SPR_SRR0:
         cpu->srr0 = cpu->gpr[rd];
         break;
      case PPC32_SPR_SRR1:
         cpu->srr1 = cpu->gpr[rd];
         break;
      case PPC32_SPR_SPRG0:
         cpu->sprg[0] = cpu->gpr[rd];
         break;
      case PPC32_SPR_SPRG1:
         cpu->sprg[1] = cpu->gpr[rd];
         break;
      case PPC32_SPR_SPRG2:
         cpu->sprg[2] = cpu->gpr[rd];
         break;
      case PPC32_SPR_SPRG3:
         cpu->sprg[3] = cpu->gpr[rd];
         break;
      case PPC32_SPR_HID0:
         cpu->hid0 = cpu->gpr[rd];
         break;
      case PPC32_SPR_HID1:
         cpu->hid1 = cpu->gpr[rd];
         break;
      case PPC405_SPR_PID:
         cpu->ppc405_pid = cpu->gpr[rd];
         break;
#if 0
      default:
         printf("WRITING SPR=%d, data=0x%8.8x\n",spr,cpu->gpr[rd]);
#endif
   }

   return(0);
}

/* MTSR - Move To Segment Register */
static fastcall int ppc32_exec_MTSR(cpu_ppc_t *cpu,ppc_insn_t insn)
{   
   int rs = bits(insn,21,25);
   int sr = bits(insn,16,19);

   cpu->sr[sr] = cpu->gpr[rs];
   ppc32_mem_invalidate_cache(cpu);
   return(0);
}

/* MULHW - Multiply High Word */
static fastcall int ppc32_exec_MULHW(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_int64_t tmp;
   m_uint32_t res;
 
   tmp =  (m_int64_t)(m_int32_t)cpu->gpr[ra];
   tmp *= (m_int64_t)(m_int32_t)cpu->gpr[rb];
   res = tmp >> 32;

   cpu->gpr[rd] = res;
   return(0);
}

/* MULHW. */
static fastcall int ppc32_exec_MULHW_dot(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_int64_t tmp;
   m_uint32_t res;
 
   tmp =  (m_int64_t)(m_int32_t)cpu->gpr[ra];
   tmp *= (m_int64_t)(m_int32_t)cpu->gpr[rb];
   res = tmp >> 32;
   ppc32_exec_update_cr0(cpu,res);
   cpu->gpr[rd] = res;
   return(0);
}

/* MULHWU - Multiply High Word Unsigned */
static fastcall int ppc32_exec_MULHWU(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint64_t tmp;
   m_uint32_t res;
 
   tmp =  (m_uint64_t)cpu->gpr[ra];
   tmp *= (m_uint64_t)cpu->gpr[rb];
   res = tmp >> 32;

   cpu->gpr[rd] = res;
   return(0);
}

/* MULHWU. */
static fastcall int ppc32_exec_MULHWU_dot(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_uint64_t tmp;
   m_uint32_t res;
 
   tmp =  (m_uint64_t)cpu->gpr[ra];
   tmp *= (m_uint64_t)cpu->gpr[rb];
   res = tmp >> 32;
   ppc32_exec_update_cr0(cpu,res);
   cpu->gpr[rd] = res;
   return(0);
}

/* MULLI - Multiply Low Immediate */
static fastcall int ppc32_exec_MULLI(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   m_uint32_t imm = bits(insn,0,15);

   cpu->gpr[rd] = (m_int32_t)cpu->gpr[ra] * sign_extend_32(imm,16);
   return(0);
}

/* MULLW - Multiply Low Word */
static fastcall int ppc32_exec_MULLW(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   m_int64_t tmp;
 
   tmp =  (m_int64_t)(m_int32_t)cpu->gpr[ra];
   tmp *= (m_int64_t)(m_int32_t)cpu->gpr[rb];
   cpu->gpr[rd] = (m_uint32_t)tmp;
   return(0);
}

/* MULLW. */
static fastcall int ppc32_exec_MULLW_dot(cpu_ppc_t *cpu,ppc_insn_t insn)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   register m_uint32_t res;
   m_int64_t tmp;
 
   tmp =  (m_int64_t)(m_int32_t)cpu->gpr[ra];
   tmp *= (m_int64_t)(m_int32_t)cpu->gpr[rb];

   res = (m_uint32_t)tmp;
   ppc32_exec_update_cr0(cpu,res);
   cpu->gpr[rd] = res;
   return(0);
}

/* MULLWO - Multiply Low Word with Overflow */
static fastcall int ppc32_exec_MULLWO(cpu_ppc_t *cpu,ppc_insn_t insn)