ppc32_amd64_trans.c

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   iop = ppc32_op_emit_insn_output(cpu,3,"crandc");

   /* test $ba bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(ba)),
                          (1 << ppc32_get_cr_bit(ba)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,AMD64_RDX,FALSE);

   /* test $bb bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bb)),
                          (1 << ppc32_get_cr_bit(bb)));
   amd64_set_reg(iop->ob_ptr,X86_CC_Z,hreg_t0,FALSE);
   
   /* result of AND between $ba and $bb */
   amd64_alu_reg_reg(iop->ob_ptr,X86_AND,hreg_t0,AMD64_RDX);
   amd64_alu_reg_imm(iop->ob_ptr,X86_AND,hreg_t0,0x01);
   
   /* set/clear $bd bit depending on the result */
   amd64_alu_membase_imm_size(iop->ob_ptr,X86_AND,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              ~(1 << ppc32_get_cr_bit(bd)),4);

   amd64_shift_reg_imm(iop->ob_ptr,X86_SHL,hreg_t0,ppc32_get_cr_bit(bd));
   amd64_alu_membase_reg_size(iop->ob_ptr,X86_OR,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              hreg_t0,4);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* CREQV - Condition Register EQV */
DECLARE_INSN(CREQV)
{
   int bd = bits(insn,21,25);
   int bb = bits(insn,16,20);
   int ba = bits(insn,11,15);
   int hreg_t0;
   jit_op_t *iop;

   ppc32_op_emit_alter_host_reg(cpu,AMD64_RDX);

   ppc32_jit_start_hreg_seq(cpu,"creqv");
   hreg_t0 = ppc32_jit_get_tmp_hreg(cpu);
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RDX);

   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(ba));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bb));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bd));

   iop = ppc32_op_emit_insn_output(cpu,3,"creqv");

   /* test $ba bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(ba)),
                          (1 << ppc32_get_cr_bit(ba)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,AMD64_RDX,FALSE);

   /* test $bb bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bb)),
                          (1 << ppc32_get_cr_bit(bb)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,hreg_t0,FALSE);
   
   /* result of XOR between $ba and $bb */
   amd64_alu_reg_reg(iop->ob_ptr,X86_XOR,hreg_t0,AMD64_RDX);
   amd64_not_reg(iop->ob_ptr,hreg_t0);
   amd64_alu_reg_imm(iop->ob_ptr,X86_AND,hreg_t0,0x01);
   
   /* set/clear $bd bit depending on the result */
   amd64_alu_membase_imm_size(iop->ob_ptr,X86_AND,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              ~(1 << ppc32_get_cr_bit(bd)),4);

   amd64_shift_reg_imm(iop->ob_ptr,X86_SHL,hreg_t0,ppc32_get_cr_bit(bd));
   amd64_alu_membase_reg_size(iop->ob_ptr,X86_OR,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              hreg_t0,4);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* CRNAND - Condition Register NAND */
DECLARE_INSN(CRNAND)
{
   int bd = bits(insn,21,25);
   int bb = bits(insn,16,20);
   int ba = bits(insn,11,15);
   int hreg_t0;
   jit_op_t *iop;

   ppc32_op_emit_alter_host_reg(cpu,AMD64_RDX);

   ppc32_jit_start_hreg_seq(cpu,"crnand");
   hreg_t0 = ppc32_jit_get_tmp_hreg(cpu);
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RDX);

   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(ba));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bb));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bd));

   iop = ppc32_op_emit_insn_output(cpu,3,"crnand");

   /* test $ba bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(ba)),
                          (1 << ppc32_get_cr_bit(ba)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,AMD64_RDX,FALSE);

   /* test $bb bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bb)),
                          (1 << ppc32_get_cr_bit(bb)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,hreg_t0,FALSE);
   
   /* result of NAND between $ba and $bb */
   amd64_alu_reg_reg(iop->ob_ptr,X86_AND,hreg_t0,AMD64_RDX);
   amd64_not_reg(iop->ob_ptr,hreg_t0);
   amd64_alu_reg_imm(iop->ob_ptr,X86_AND,hreg_t0,0x01);
   
   /* set/clear $bd bit depending on the result */
   amd64_alu_membase_imm_size(iop->ob_ptr,X86_AND,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              ~(1 << ppc32_get_cr_bit(bd)),4);

   amd64_shift_reg_imm(iop->ob_ptr,X86_SHL,hreg_t0,ppc32_get_cr_bit(bd));
   amd64_alu_membase_reg_size(iop->ob_ptr,X86_OR,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              hreg_t0,4);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* CRNOR - Condition Register NOR */
DECLARE_INSN(CRNOR)
{
   int bd = bits(insn,21,25);
   int bb = bits(insn,16,20);
   int ba = bits(insn,11,15);
   int hreg_t0;
   jit_op_t *iop;

   ppc32_op_emit_alter_host_reg(cpu,AMD64_RDX);

   ppc32_jit_start_hreg_seq(cpu,"crnor");
   hreg_t0 = ppc32_jit_get_tmp_hreg(cpu);
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RDX);

   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(ba));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bb));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bd));

   iop = ppc32_op_emit_insn_output(cpu,3,"crnor");

   /* test $ba bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(ba)),
                          (1 << ppc32_get_cr_bit(ba)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,AMD64_RDX,FALSE);

   /* test $bb bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bb)),
                          (1 << ppc32_get_cr_bit(bb)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,hreg_t0,FALSE);
   
   /* result of NOR between $ba and $bb */
   amd64_alu_reg_reg(iop->ob_ptr,X86_OR,hreg_t0,AMD64_RDX);
   amd64_not_reg(iop->ob_ptr,hreg_t0);
   amd64_alu_reg_imm(iop->ob_ptr,X86_AND,hreg_t0,0x01);
   
   /* set/clear $bd bit depending on the result */
   amd64_alu_membase_imm_size(iop->ob_ptr,X86_AND,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              ~(1 << ppc32_get_cr_bit(bd)),4);

   amd64_shift_reg_imm(iop->ob_ptr,X86_SHL,hreg_t0,ppc32_get_cr_bit(bd));
   amd64_alu_membase_reg_size(iop->ob_ptr,X86_OR,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              hreg_t0,4);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* CROR - Condition Register OR */
DECLARE_INSN(CROR)
{
   int bd = bits(insn,21,25);
   int bb = bits(insn,16,20);
   int ba = bits(insn,11,15);
   int hreg_t0;
   jit_op_t *iop;

   ppc32_op_emit_alter_host_reg(cpu,AMD64_RDX);

   ppc32_jit_start_hreg_seq(cpu,"cror");
   hreg_t0 = ppc32_jit_get_tmp_hreg(cpu);
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RDX);

   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(ba));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bb));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bd));

   iop = ppc32_op_emit_insn_output(cpu,3,"cror");

   /* test $ba bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(ba)),
                          (1 << ppc32_get_cr_bit(ba)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,AMD64_RDX,FALSE);

   /* test $bb bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bb)),
                          (1 << ppc32_get_cr_bit(bb)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,hreg_t0,FALSE);
   
   /* result of NOR between $ba and $bb */
   amd64_alu_reg_reg(iop->ob_ptr,X86_OR,hreg_t0,AMD64_RDX);
   amd64_alu_reg_imm(iop->ob_ptr,X86_AND,hreg_t0,0x01);
   
   /* set/clear $bd bit depending on the result */
   amd64_alu_membase_imm_size(iop->ob_ptr,X86_AND,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              ~(1 << ppc32_get_cr_bit(bd)),4);

   amd64_shift_reg_imm(iop->ob_ptr,X86_SHL,hreg_t0,ppc32_get_cr_bit(bd));
   amd64_alu_membase_reg_size(iop->ob_ptr,X86_OR,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              hreg_t0,4);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* CRORC - Condition Register OR with Complement */
DECLARE_INSN(CRORC)
{
   int bd = bits(insn,21,25);
   int bb = bits(insn,16,20);
   int ba = bits(insn,11,15);
   int hreg_t0;
   jit_op_t *iop;

   ppc32_op_emit_alter_host_reg(cpu,AMD64_RDX);

   ppc32_jit_start_hreg_seq(cpu,"crorc");
   hreg_t0 = ppc32_jit_get_tmp_hreg(cpu);
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RDX);

   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(ba));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bb));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bd));

   iop = ppc32_op_emit_insn_output(cpu,3,"crorc");

   /* test $ba bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(ba)),
                          (1 << ppc32_get_cr_bit(ba)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,AMD64_RDX,FALSE);

   /* test $bb bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bb)),
                          (1 << ppc32_get_cr_bit(bb)));
   amd64_set_reg(iop->ob_ptr,X86_CC_Z,hreg_t0,FALSE);
   
   /* result of ORC between $ba and $bb */
   amd64_alu_reg_reg(iop->ob_ptr,X86_OR,hreg_t0,AMD64_RDX);
   amd64_alu_reg_imm(iop->ob_ptr,X86_AND,hreg_t0,0x01);
   
   /* set/clear $bd bit depending on the result */
   amd64_alu_membase_imm_size(iop->ob_ptr,X86_AND,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              ~(1 << ppc32_get_cr_bit(bd)),4);

   amd64_shift_reg_imm(iop->ob_ptr,X86_SHL,hreg_t0,ppc32_get_cr_bit(bd));
   amd64_alu_membase_reg_size(iop->ob_ptr,X86_OR,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              hreg_t0,4);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* CRXOR - Condition Register XOR */
DECLARE_INSN(CRXOR)
{
   int bd = bits(insn,21,25);
   int bb = bits(insn,16,20);
   int ba = bits(insn,11,15);
   int hreg_t0;
   jit_op_t *iop;

   ppc32_op_emit_alter_host_reg(cpu,AMD64_RDX);

   ppc32_jit_start_hreg_seq(cpu,"crxor");
   hreg_t0 = ppc32_jit_get_tmp_hreg(cpu);
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RDX);

   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(ba));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bb));
   ppc32_op_emit_require_flags(cpu,ppc32_get_cr_field(bd));

   iop = ppc32_op_emit_insn_output(cpu,3,"crxor");

   /* test $ba bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(ba)),
                          (1 << ppc32_get_cr_bit(ba)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,AMD64_RDX,FALSE);

   /* test $bb bit */
   amd64_test_membase_imm(iop->ob_ptr,
                          AMD64_R15,
                          PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bb)),
                          (1 << ppc32_get_cr_bit(bb)));
   amd64_set_reg(iop->ob_ptr,X86_CC_NZ,hreg_t0,FALSE);
   
   /* result of XOR between $ba and $bb */
   amd64_alu_reg_reg(iop->ob_ptr,X86_XOR,hreg_t0,AMD64_RDX);
   amd64_alu_reg_imm(iop->ob_ptr,X86_AND,hreg_t0,0x01);
   
   /* set/clear $bd bit depending on the result */
   amd64_alu_membase_imm_size(iop->ob_ptr,X86_AND,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              ~(1 << ppc32_get_cr_bit(bd)),4);

   amd64_shift_reg_imm(iop->ob_ptr,X86_SHL,hreg_t0,ppc32_get_cr_bit(bd));
   amd64_alu_membase_reg_size(iop->ob_ptr,X86_OR,
                              AMD64_R15,
                              PPC32_CR_FIELD_OFFSET(ppc32_get_cr_field(bd)),
                              hreg_t0,4);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* DIVWU - Divide Word Unsigned */
DECLARE_INSN(DIVWU)
{
   int rd = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   int hreg_rb;
   jit_op_t *iop;

   ppc32_jit_start_hreg_seq(cpu,"divwu");
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RAX);
   ppc32_jit_alloc_hreg_forced(cpu,AMD64_RDX);
   hreg_rb = ppc32_jit_alloc_hreg(cpu,rb);

   /* $rd = $ra / $rb */
   ppc32_op_emit_load_gpr(cpu,AMD64_RAX,ra);
   ppc32_op_emit_load_gpr(cpu,hreg_rb,rb);

   iop = ppc32_op_emit_insn_output(cpu,2,"divwu");
   ppc32_load_imm(&iop->ob_ptr,AMD64_RDX,0);

   amd64_div_reg_size(iop->ob_ptr,hreg_rb,0,4);

   if (insn & 1)
      amd64_test_reg_reg_size(iop->ob_ptr,AMD64_RAX,AMD64_RAX,4);

   ppc32_op_emit_store_gpr(cpu,rd,AMD64_RAX);

   if (insn & 1)
      ppc32_op_emit_update_flags(cpu,0,TRUE);

   /* edx:eax are directly modified: throw them */
   ppc32_op_emit_alter_host_reg(cpu,AMD64_RAX);
   ppc32_op_emit_alter_host_reg(cpu,AMD64_RDX);

   ppc32_jit_close_hreg_seq(cpu);
   return(0);
}

/* EQV */
DECLARE_INSN(EQV)
{
   int rs = bits(insn,21,25);
   int ra = bits(insn,16,20);
   int rb = bits(insn,11,15);
   int hreg_rs,hreg_ra,hreg_rb;
   jit_op_t *iop;

   /* $ra = ~($rs ^ $rb) */
   ppc32_jit_start_hreg_seq(cpu,"eqv");
   hreg_rs = ppc32_jit_alloc_hreg(cpu,rs);
   hreg_ra = ppc32_jit_alloc_hreg(cpu,ra);
   hreg_rb = ppc32_jit_alloc_hreg(cpu,rb);

   ppc32_op_emit_load_gpr(cpu,hreg_rs,rs);
   ppc32_op_emit_load_gpr(cpu,hreg_rb,rb);

   iop = ppc32_op_emit_insn_output(cpu,1,"eqv");

   if (ra == rs)
      amd64_alu_reg_reg_size(iop->ob_ptr,X86_XOR,hreg_ra,hreg_rb,4);
   else if (ra == rb)
      amd64_alu_reg