mips64_exec.c

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   val = (m_uint64_t)(m_uint32_t)cpu->gpr[rs];
   val *= (m_uint64_t)(m_uint32_t)cpu->gpr[rt];
   cpu->lo = sign_extend(val,32);
   cpu->hi = sign_extend(val >> 32,32);
   return(0);
}

/* NOP */
static fastcall int mips64_exec_NOP(cpu_mips_t *cpu,mips_insn_t insn)
{
   return(0);
}

/* NOR */
static fastcall int mips64_exec_NOR(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);

   cpu->gpr[rd] = ~(cpu->gpr[rs] | cpu->gpr[rt]);
   return(0);
}

/* OR */
static fastcall int mips64_exec_OR(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);

   cpu->gpr[rd] = cpu->gpr[rs] | cpu->gpr[rt];
   return(0);
}

/* ORI */
static fastcall int mips64_exec_ORI(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs  = bits(insn,21,25);
   int rt  = bits(insn,16,20);
   int imm = bits(insn,0,15);

   cpu->gpr[rt] = cpu->gpr[rs] | imm;
   return(0);
}

/* PREF */
static fastcall int mips64_exec_PREF(cpu_mips_t *cpu,mips_insn_t insn)
{
   return(0);
}

/* PREFI */
static fastcall int mips64_exec_PREFI(cpu_mips_t *cpu,mips_insn_t insn)
{
   return(0);
}

/* SB (Store Byte) */
static fastcall int mips64_exec_SB(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SB,base,offset,rt,FALSE);
   return(0);
}

/* SC (Store Conditional) */
static fastcall int mips64_exec_SC(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SC,base,offset,rt,TRUE);
   return(0);
}

/* SD (Store Double-Word) */
static fastcall int mips64_exec_SD(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SD,base,offset,rt,FALSE);
   return(0);
}

/* SDL (Store Double-Word Left) */
static fastcall int mips64_exec_SDL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);
   
   mips64_exec_memop2(cpu,MIPS_MEMOP_SDL,base,offset,rt,FALSE);
   return(0);
}

/* SDR (Store Double-Word Right) */
static fastcall int mips64_exec_SDR(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SDR,base,offset,rt,FALSE);
   return(0);
}

/* SDC1 (Store Double-Word from Coprocessor 1) */
static fastcall int mips64_exec_SDC1(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int ft     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SDC1,base,offset,ft,FALSE);
   return(0);
}

/* SH (Store Half-Word) */
static fastcall int mips64_exec_SH(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SH,base,offset,rt,FALSE);
   return(0);
}

/* SLL */
static fastcall int mips64_exec_SLL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   int sa = bits(insn,6,10);
   m_uint32_t res;
   
   res = (m_uint32_t)cpu->gpr[rt] << sa;
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SLLV */
static fastcall int mips64_exec_SLLV(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   m_uint32_t res;
   
   res = (m_uint32_t)cpu->gpr[rt] << (cpu->gpr[rs] & 0x1f);
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SLT */
static fastcall int mips64_exec_SLT(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);

   if ((m_int64_t)cpu->gpr[rs] < (m_int64_t)cpu->gpr[rt])
      cpu->gpr[rd] = 1;
   else
      cpu->gpr[rd] = 0;

   return(0);
}

/* SLTI */
static fastcall int mips64_exec_SLTI(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int imm = bits(insn,0,15);
   m_int64_t val = sign_extend(imm,16);

   if ((m_int64_t)cpu->gpr[rs] < val)
      cpu->gpr[rt] = 1;
   else
      cpu->gpr[rt] = 0;

   return(0);
}

/* SLTIU */
static fastcall int mips64_exec_SLTIU(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int imm = bits(insn,0,15);
   m_uint64_t val = sign_extend(imm,16);

   if (cpu->gpr[rs] < val)
      cpu->gpr[rt] = 1;
   else
      cpu->gpr[rt] = 0;

   return(0);
}

/* SLTU */
static fastcall int mips64_exec_SLTU(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);

   if (cpu->gpr[rs] < cpu->gpr[rt])
      cpu->gpr[rd] = 1;
   else
      cpu->gpr[rd] = 0;

   return(0);
}

/* SRA */
static fastcall int mips64_exec_SRA(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   int sa = bits(insn,6,10);
   m_int32_t res;
   
   res = (m_int32_t)cpu->gpr[rt] >> sa;
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SRAV */
static fastcall int mips64_exec_SRAV(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   m_int32_t res;
   
   res = (m_int32_t)cpu->gpr[rt] >> (cpu->gpr[rs] & 0x1f);
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SRL */
static fastcall int mips64_exec_SRL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   int sa = bits(insn,6,10);
   m_uint32_t res;
   
   res = (m_uint32_t)cpu->gpr[rt] >> sa;
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SRLV */
static fastcall int mips64_exec_SRLV(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   m_uint32_t res;
   
   res = (m_uint32_t)cpu->gpr[rt] >> (cpu->gpr[rs] & 0x1f);
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SUB */
static fastcall int mips64_exec_SUB(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   m_uint32_t res;

   /* TODO: Exception handling */
   res = (m_uint32_t)cpu->gpr[rs] - (m_uint32_t)cpu->gpr[rt];
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SUBU */
static fastcall int mips64_exec_SUBU(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);
   m_uint32_t res;

   res = (m_uint32_t)cpu->gpr[rs] - (m_uint32_t)cpu->gpr[rt];
   cpu->gpr[rd] = sign_extend(res,32);
   return(0);
}

/* SW (Store Word) */
static fastcall int mips64_exec_SW(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SW,base,offset,rt,FALSE);
   return(0);
}

/* SWL (Store Word Left) */
static fastcall int mips64_exec_SWL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);
   
   mips64_exec_memop2(cpu,MIPS_MEMOP_SWL,base,offset,rt,FALSE);
   return(0);
}

/* SWR (Store Word Right) */
static fastcall int mips64_exec_SWR(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int rt     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_SWR,base,offset,rt,FALSE);
   return(0);
}

/* SYNC */
static fastcall int mips64_exec_SYNC(cpu_mips_t *cpu,mips_insn_t insn)
{
   return(0);
}

/* SYSCALL */
static fastcall int mips64_exec_SYSCALL(cpu_mips_t *cpu,mips_insn_t insn)
{
   mips64_exec_syscall(cpu);
   return(1);
}

/* TEQ (Trap if Equal) */
static fastcall int mips64_exec_TEQ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);

   if (unlikely(cpu->gpr[rs] == cpu->gpr[rt])) {
      mips64_trigger_trap_exception(cpu);
      return(1);
   }

   return(0);
}

/* TEQI (Trap if Equal Immediate) */
static fastcall int mips64_exec_TEQI(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int imm = bits(insn,0,15);
   m_uint64_t val = sign_extend(imm,16);

   if (unlikely(cpu->gpr[rs] == val)) {
      mips64_trigger_trap_exception(cpu);
      return(1);
   }

   return(0);
}

/* TLBP */
static fastcall int mips64_exec_TLBP(cpu_mips_t *cpu,mips_insn_t insn)
{
   mips64_cp0_exec_tlbp(cpu);
   return(0);
}

/* TLBR */
static fastcall int mips64_exec_TLBR(cpu_mips_t *cpu,mips_insn_t insn)
{
   mips64_cp0_exec_tlbr(cpu);
   return(0);
}

/* TLBWI */
static fastcall int mips64_exec_TLBWI(cpu_mips_t *cpu,mips_insn_t insn)
{
   mips64_cp0_exec_tlbwi(cpu);
   return(0);
}

/* TLBWR */
static fastcall int mips64_exec_TLBWR(cpu_mips_t *cpu,mips_insn_t insn)
{
   mips64_cp0_exec_tlbwr(cpu);
   return(0);
}

/* XOR */
static fastcall int mips64_exec_XOR(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);

   cpu->gpr[rd] = cpu->gpr[rs] ^ cpu->gpr[rt];
   return(0);
}

/* XORI */
static fastcall int mips64_exec_XORI(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs  = bits(insn,21,25);
   int rt  = bits(insn,16,20);
   int imm = bits(insn,0,15);

   cpu->gpr[rt] = cpu->gpr[rs] ^ imm;
   return(0);
}

/* MIPS instruction array */
static struct mips64_insn_exec_tag mips64_exec_tags[] = {
   { "li"     , mips64_exec_LI      , 0xffe00000 , 0x24000000, 1, 16 },
   { "move"   , mips64_exec_MOVE    , 0xfc1f07ff , 0x00000021, 1, 15 },
   { "b"      , mips64_exec_B       , 0xffff0000 , 0x10000000, 0, 10 },
   { "bal"    , mips64_exec_BAL     , 0xffff0000 , 0x04110000, 0, 10 },
   { "beqz"   , mips64_exec_BEQZ    , 0xfc1f0000 , 0x10000000, 0, 9 },
   { "bnez"   , mips64_exec_BNEZ    , 0xfc1f0000 , 0x14000000, 0, 9 },
   { "add"    , mips64_exec_ADD     , 0xfc0007ff , 0x00000020, 1, 3 },
   { "addi"   , mips64_exec_ADDI    , 0xfc000000 , 0x20000000, 1, 6 },
   { "addiu"  , mips64_exec_ADDIU   , 0xfc000000 , 0x24000000, 1, 6 },
   { "addu"   , mips64_exec_ADDU    , 0xfc0007ff , 0x00000021, 1, 3 },
   { "and"    , mips64_exec_AND     , 0xfc0007ff , 0x00000024, 1, 3 },
   { "andi"   , mips64_exec_ANDI    , 0xfc000000 , 0x30000000, 1, 5 },
   { "beq"    , mips64_exec_BEQ     , 0xfc000000 , 0x10000000, 0, 8 },
   { "beql"   , mips64_exec_BEQL    , 0xfc000000 , 0x50000000, 0, 8 },
   { "bgez"   , mips64_exec_BGEZ    , 0xfc1f0000 , 0x04010000, 0, 9 },
   { "bgezal" , mips64_exec_BGEZAL  , 0xfc1f0000 , 0x04110000, 0, 9 },
   { "bgezall", mips64_exec_BGEZALL , 0xfc1f0000 , 0x04130000, 0, 9 },
   { "bgezl"  , mips64_exec_BGEZL   , 0xfc1f0000 , 0x04030000, 0, 9 },
   { "bgtz"   , mips64_exec_BGTZ    , 0xfc1f0000 , 0x1c000000, 0, 9 },
   { "bgtzl"  , mips64_exec_BGTZL   , 0xfc1f0000 , 0x5c000000, 0, 9 },
   { "blez"   , mips64_exec_BLEZ    , 0xfc1f0000 , 0x18000000, 0, 9 },
   { "blezl"  , mips64_exec_BLEZL   , 0xfc1f0000 , 0x58000000, 0, 9 },
   { "bltz"   , mips64_exec_BLTZ    , 0xfc1f0000 , 0x04000000, 0, 9 },
   { "bltzal" , mips64_exec_BLTZAL  , 0xfc1f0000 , 0x04100000, 0, 9 },
   { "bltzall", mips64_exec_BLTZALL , 0xfc1f0000 , 0x04120000, 0, 9 },
   { "bltzl"  , mips64_exec_BLTZL   , 0xfc1f0000 , 0x04020000, 0, 9 },
   { "bne"    , mips64_exec_BNE     , 0xfc000000 , 0x14000000, 0, 8 },
   { "bnel"   , mips64_exec_BNEL    , 0xfc000000 , 0x54000000, 0, 8 },
   { "break"  , mips64_exec_BREAK   , 0xfc00003f , 0x0000000d, 1, 0 },
   { "cache"  , mips64_exec_CACHE   , 0xfc000000 , 0xbc000000, 1, 2 },
   { "cfc0"   , mips64_exec_CFC0    , 0xffe007ff , 0x40400000, 1, 18 },
   { "ctc0"   , mips64_exec_CTC0    , 0xffe007ff , 0x40600000, 1, 18 },
   { "daddiu" , mips64_exec_DADDIU  , 0xfc000000 , 0x64000000, 1, 5 },
   { "daddu"  , mips64_exec_DADDU   , 0xfc0007ff , 0x0000002d, 1, 3 },
   { "div"    , mips64_exec_DIV     , 0xfc00ffff , 0x0000001a, 1, 17 },
   { "divu"   , mips64_exec_DIVU    , 0xfc00ffff , 0x0000001b, 1, 17 },
   { "dmfc0"  , mips64_exec_DMFC0   , 0xffe007f8 , 0x40200000, 1, 18 },
   { "dmfc1"  , mips64_exec_DMFC1   , 0xffe007ff , 0x44200000, 1, 19 },
   { "dmtc0"  , mips64_exec_DMTC0   , 0xffe007f8 , 0x40a00000, 1, 18 },
   { "dmtc1"  , mips64_exec_DMTC1   , 0xffe007ff , 0x44a00000, 1, 19 },
   { "dsll"   , mips64_exec_DSLL    , 0xffe0003f , 0x00000038, 1, 7 },
   { "dsll32" , mips64_exec_DSLL32  , 0xffe0003f , 0x0000003c, 1, 7 },
   { "dsllv"  , mips64_exec_DSLLV   , 0xfc0007ff , 0x00000014, 1, 4 },
   { "dsra"   , mips64_exec_DSRA    , 0xffe0003f , 0x0000003b, 1, 7 },
   { "dsra32" , mips64_exec_DSRA32  , 0xffe0003f , 0x0000003f, 1, 7 },
   { "dsrav"  , mips64_exec_DSRAV   , 0xfc0007ff , 0x00000017, 1, 4 },
   { "dsrl"   , mips64_exec_DSRL    , 0xffe0003f , 0x0000003a, 1, 7 },
   { "dsrl32" , mips64_exec_DSRL32  , 0xffe0003f , 0x0000003e, 1, 7 },
   { "dsrlv"  , mips64_exec_DSRLV   , 0xfc0007ff , 0x00000016, 1, 4 },
   { "dsubu"  , mips64_exec_DSUBU   , 0xfc0007ff , 0x0000002f, 1, 3 },
   { "eret"   , mips64_exec_ERET    , 0xffffffff , 0x42000018, 0, 1 },
   { "j"      , mips64_exec_J       , 0xfc000000 , 0x08000000, 0, 11 },
   { "jal"    , mips64_exec_JAL     , 0xfc000000 , 0x0c000000, 0, 11 },
   { "jalr"   , mips64_exec_JALR    , 0xfc1f003f , 0x00000009, 0, 15 },
   { "jr"     , mips64_exec_JR      , 0xfc1ff83f , 0x00000008, 0, 13 },
   { "lb"     , mips64_exec_LB      , 0xfc000000 , 0x80000000, 1, 2 },
   { "lbu"    , mips64_exec_LBU     , 0xfc000000 , 0x90000000, 1, 2 },
   { "ld"     , mips64_exec_LD      , 0xfc000000 , 0xdc000000, 1, 2 },
   { "ldc1"   , mips64_exec_LDC1    , 0xfc000000 , 0xd4000000, 1, 3 },
   { "ldl"    , mips64_exec_LDL     , 0xfc000000 , 0x68000000, 1, 2 },
   { "ldr"    , mips64_exec_LDR     , 0xfc000000 , 0x6c000000, 1, 2 },
   { "lh"     , mips64_exec_LH      , 0xfc000000 , 0x84000000, 1, 2 },
   { "lhu"    , mips64_exec_LHU     , 0xfc000000 , 0x94000000, 1, 2 },
   { "ll"     , mips64_exec_LL      , 0xfc000000 , 0xc0000000, 1, 2 },
   { "lui"    , mips64_exec_LUI     , 0xffe00000 , 0x3c000000, 1, 16 },
   { "lw"     , mips64_exec_LW      , 0xfc000000 , 0x8c000000, 1, 2 },
   { "lwl"    , mips64_exec_LWL     , 0xfc000000 , 0x88000000, 1, 2 },
   { "lwr"    , mips64_exec_LWR     , 0xfc000000 , 0x98000000, 1, 2 },
   { "lwu"    , mips64_exec_LWU     , 0xfc000000 , 0x9c000000, 1, 2 },
   { "mfc0"   , mips64_exec_MFC0    , 0xffe007ff , 0x40000000, 1, 18 },
   { "mfc0_1" , mips64_exec_CFC0    , 0xffe007ff , 0x40000001, 1, 19 },
   { "mfc1"   , mips64_exec_MFC1    , 0xffe007ff , 0x44000000, 1, 19 },
   { "mfhi"   , mips64_exec_MFHI    , 0xffff07ff , 0x00000010, 1, 14 },
   { "mflo"   , mips64_exec_MFLO    , 0xffff07ff , 0x00000012, 1, 14 },
   { "mtc0"   , mips64_exec_MTC0    , 0xffe007ff , 0x40800000, 1, 18 },
   { "mtc1"   , mips64_exec_MTC1    , 0xffe007ff , 0x44800000, 1, 19 },
   { "mthi"   , mips64_exec_MTHI    , 0xfc1fffff , 0x00000011, 1, 13 },
   { "mtlo"   , mips64_exec_MTLO    , 0xfc1fffff , 0x00000013, 1, 13 },
   { "mul"    , mips64_exec_MUL     , 0xfc0007ff , 0x70000002, 1, 4 },
   { "mult"   , mips64_exec_MULT    , 0xfc00ffff , 0x00000018, 1, 17 },
   { "multu"  , mips64_exec_MULTU   , 0xfc00ffff , 0x00000019, 1, 17 },
   { "nop"    , mips64_exec_NOP     , 0xffffffff , 0x00000000, 1, 1 },
   { "nor"    , mips64_exec_NOR     , 0xfc0007ff , 0x00000027, 1, 3 },
   { "or"     , mips64_exec_OR      , 0xfc0007ff , 0x00000025, 1, 3 },
   { "ori"    , mips64_exec_ORI     , 0xfc000000 , 0x34000000, 1, 5 },
   { "pref"   , mips64_exec_PREF    , 0xfc000000 , 0xcc000000, 1, 0 },
   { "prefi"  , mips64_exec_PREFI   , 0xfc0007ff , 0x4c00000f, 1, 0 },
   { "sb"     , mips64_exec_SB      , 0xfc000000 , 0xa0000000, 1, 2 },
   { "sc"     , mips64_exec_SC      , 0xfc000000 , 0xe0000000, 1, 2 },
   { "sd"     , mips64_exec_SD      , 0xfc000000 , 0xfc000000, 1, 2 },
   { "sdc1"   , mips64_exec_SDC1    , 0xfc000000 , 0xf4000000, 1, 3 },
   { "sdl"    , mips64_exec_SDL     , 0xfc000000 , 0xb0000000, 1, 2 },
   { "sdr"    , mips64_exec_SDR     , 0xfc000000 , 0xb4000000, 1, 2 },
   { "sh"     , mips64_exec_SH      , 0xfc000000 , 0xa4000000, 1, 2 },
   { "sll"    , mips64_exec_SLL     , 0xffe0003f , 0x00000000, 1, 7 },
   { "sllv"   , mips64_exec_SLLV    , 0xfc0007ff , 0x00000004, 1, 4 },
   { "slt"    , mips64_exec_SLT     , 0xfc0007ff , 0x0000002a, 1, 3 },
   { "slti"   , mips64_exec_SLTI    , 0xfc000000 , 0x28000000, 1, 5 },
   { "sltiu"  , mips64_exec_SLTIU   , 0xfc000000 , 0x2c000000, 1, 5 },
   { "sltu"   , mips64_exec_SLTU    , 0xfc0007ff , 0x0000002b, 1, 3 },
   { "sra"    , mips64_exec_SRA     , 0xffe0003f , 0x00000003, 1, 7 },
   { "srav"   , mips64_exec_SRAV    , 0xfc0007ff , 0x00000007, 1, 4 },
   { "srl"    , mips64_exec_SRL     , 0xffe0003f , 0x00000002, 1, 7 },
   { "srlv"   , mips64_exec_SRLV    , 0xfc0007ff , 0x00000006, 1, 4 },
   { "sub"    , mips64_exec_SUB     , 0xfc0007ff , 0x00000022, 1, 3 },
   { "subu"   , mips64_exec_SUBU    , 0xfc0007ff , 0x00000023, 1, 3 },
   { "sw"     , mips64_exec_SW      , 0xfc000000 , 0xac000000, 1, 2 },
   { "swl"    , mips64_exec_SWL     , 0xfc000000 , 0xa8000000, 1, 2 },
   { "swr"    , mips64_exec_SWR     , 0xfc000000 , 0xb8000000, 1, 2 },
   { "sync"   , mips64_exec_SYNC    , 0xfffff83f , 0x0000000f, 1, 1 },
   { "syscall", mips64_exec_SYSCALL , 0xfc00003f , 0x0000000c, 1, 1 },
   { "teq"    , mips64_exec_TEQ     , 0xfc00003f , 0x00000034, 1, 17 },
   { "teqi"   , mips64_exec_TEQI    , 0xfc1f0000 , 0x040c0000, 1, 20 },
   { "tlbp"   , mips64_exec_TLBP    , 0xffffffff , 0x42000008, 1, 1 },
   { "tlbr"   , mips64_exec_TLBR    , 0xffffffff , 0x42000001, 1, 1 },
   { "tlbwi"  , mips64_exec_TLBWI   , 0xffffffff , 0x42000002, 1, 1 },
   { "tlbwr"  , mips64_exec_TLBWR   , 0xffffffff , 0x42000006, 1, 1 },
   { "xor"    , mips64_exec_XOR     , 0xfc0007ff , 0x00000026, 1, 3 },
   { "xori"   , mips64_exec_XORI    , 0xfc000000 , 0x38000000, 1, 5 },
   { "unknown", mips64_exec_unknown , 0x00000000 , 0x00000000, 1, 0 },
   { NULL     , NULL                , 0x00000000 , 0x00000000, 1, 0 },
};

#endif