mips64_exec.c

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static fastcall int mips64_exec_B(cpu_mips_t *cpu,mips_insn_t insn)
{
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* set the new pc in cpu structure */
   cpu->pc = new_pc;
   return(1);
}

/* BAL (Branch And Link, virtual instruction) */
static fastcall int mips64_exec_BAL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* set the return address (instruction after the delay slot) */
   cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8;

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* set the new pc in cpu structure */
   cpu->pc = new_pc;
   return(1);
}

/* BEQ (Branch On Equal) */
static fastcall int mips64_exec_BEQ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] == gpr[rt] */
   res = (cpu->gpr[rs] == cpu->gpr[rt]);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BEQL (Branch On Equal Likely) */
static fastcall int mips64_exec_BEQL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] == gpr[rt] */
   res = (cpu->gpr[rs] == cpu->gpr[rt]);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BEQZ (Branch On Equal Zero) - Virtual Instruction */
static fastcall int mips64_exec_BEQZ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] == 0 */
   res = (cpu->gpr[rs] == 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BNEZ (Branch On Not Equal Zero) - Virtual Instruction */
static fastcall int mips64_exec_BNEZ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] != 0 */
   res = (cpu->gpr[rs] != 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BGEZ (Branch On Greater or Equal Than Zero) */
static fastcall int mips64_exec_BGEZ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] >= 0 */
   res = ((m_int64_t)cpu->gpr[rs] >= 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BGEZAL (Branch On Greater or Equal Than Zero And Link) */
static fastcall int mips64_exec_BGEZAL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* set the return address (instruction after the delay slot) */
   cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8;

   /* take the branch if gpr[rs] >= 0 */
   res = ((m_int64_t)cpu->gpr[rs] >= 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BGEZALL (Branch On Greater or Equal Than Zero And Link Likely) */
static fastcall int mips64_exec_BGEZALL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* set the return address (instruction after the delay slot) */
   cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8;

   /* take the branch if gpr[rs] >= 0 */
   res = ((m_int64_t)cpu->gpr[rs] >= 0);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BGEZL (Branch On Greater or Equal Than Zero Likely) */
static fastcall int mips64_exec_BGEZL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] >= 0 */
   res = ((m_int64_t)cpu->gpr[rs] >= 0);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BGTZ (Branch On Greater Than Zero) */
static fastcall int mips64_exec_BGTZ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] > 0 */
   res = ((m_int64_t)cpu->gpr[rs] > 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BGTZL (Branch On Greater Than Zero Likely) */
static fastcall int mips64_exec_BGTZL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] > 0 */
   res = ((m_int64_t)cpu->gpr[rs] > 0);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BLEZ (Branch On Less or Equal Than Zero) */
static fastcall int mips64_exec_BLEZ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] <= 0 */
   res = ((m_int64_t)cpu->gpr[rs] <= 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BLEZL (Branch On Less or Equal Than Zero Likely) */
static fastcall int mips64_exec_BLEZL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] <= 0 */
   res = ((m_int64_t)cpu->gpr[rs] <= 0);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BLTZ (Branch On Less Than Zero) */
static fastcall int mips64_exec_BLTZ(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] < 0 */
   res = ((m_int64_t)cpu->gpr[rs] < 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res)
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BLTZAL (Branch On Less Than Zero And Link) */
static fastcall int mips64_exec_BLTZAL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* set the return address (instruction after the delay slot) */
   cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8;

   /* take the branch if gpr[rs] < 0 */
   res = ((m_int64_t)cpu->gpr[rs] < 0);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res)
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BLTZALL (Branch On Less Than Zero And Link Likely) */
static fastcall int mips64_exec_BLTZALL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* set the return address (instruction after the delay slot) */
   cpu->gpr[MIPS_GPR_RA] = cpu->pc + 8;

   /* take the branch if gpr[rs] < 0 */
   res = ((m_int64_t)cpu->gpr[rs] < 0);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BLTZL (Branch On Less Than Zero Likely) */
static fastcall int mips64_exec_BLTZL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] < 0 */
   res = ((m_int64_t)cpu->gpr[rs] < 0);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BNE (Branch On Not Equal) */
static fastcall int mips64_exec_BNE(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] != gpr[rt] */
   res = (cpu->gpr[rs] != cpu->gpr[rt]);

   /* exec the instruction in the delay slot */
   mips64_exec_bdslot(cpu);

   /* take the branch if the test result is true */
   if (res) 
      cpu->pc = new_pc;
   else
      cpu->pc += 8;

   return(1);
}

/* BNEL (Branch On Not Equal Likely) */
static fastcall int mips64_exec_BNEL(cpu_mips_t *cpu,mips_insn_t insn)
{
   int rs = bits(insn,21,25);
   int rt = bits(insn,16,20);
   int offset = bits(insn,0,15);
   m_uint64_t new_pc;
   int res;

   /* compute the new pc */
   new_pc = (cpu->pc + 4) + sign_extend(offset << 2,18);

   /* take the branch if gpr[rs] != gpr[rt] */
   res = (cpu->gpr[rs] != cpu->gpr[rt]);

   /* take the branch if the test result is true */
   if (res) {
      mips64_exec_bdslot(cpu);
      cpu->pc = new_pc;
   } else
      cpu->pc += 8;

   return(1);
}

/* BREAK */
static fastcall int mips64_exec_BREAK(cpu_mips_t *cpu,mips_insn_t insn)
{
   u_int code = bits(insn,6,25);

   mips64_exec_break(cpu,code);
   return(1);
}

/* CACHE */
static fastcall int mips64_exec_CACHE(cpu_mips_t *cpu,mips_insn_t insn)
{
   int base   = bits(insn,21,25);
   int op     = bits(insn,16,20);
   int offset = bits(insn,0,15);

   mips64_exec_memop2(cpu,MIPS_MEMOP_CACHE,base,offset,op,FALSE);
   return(0);
}

/* CFC0 */
static fastcall int mips64_exec_CFC0(cpu_mips_t *cpu,mips_insn_t insn)
{	
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);

   mips64_cp0_exec_cfc0(cpu,rt,rd);
   return(0);
}

/* CTC0 */
static fastcall int mips64_exec_CTC0(cpu_mips_t *cpu,mips_insn_t insn)
{	
   int rt = bits(insn,16,20);
   int rd = bits(insn,11,15);

   mips64_cp0_exec_ctc0(cpu,rt,rd);
   return(0);
}

/* DADDIU */
static fastcall int mips64_exec_DADDIU(cpu_mips_t *cpu,mips_insn_t insn)
{	
   int rs  = bits(insn,21,25);
   int rt  = bits(insn,16,20);
   int imm = bits(insn,0,15);
   m_uint64_t val = sign_extend(imm,16);

   cpu->gpr[rt] = cpu->gpr[rs] + val;
   return(0);
}

/* DADDU: rd = rs + rt */
static fastcall int mips64_exec_DADDU(cpu_mips_t *cpu,mips_insn_t insn)