mips64.h

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   MIPS_MEMOP_SDC1,

   MIPS_MEMOP_CACHE,

   MIPS_MEMOP_MAX,
};

/* Maximum number of breakpoints */
#define MIPS64_MAX_BREAKPOINTS  8

/* MIPS CPU type */
typedef struct cpu_mips cpu_mips_t;

/* Memory operation function prototype */
typedef fastcall void (*mips_memop_fn)(cpu_mips_t *cpu,m_uint64_t vaddr,
                                       u_int reg);

/* TLB entry definition */
typedef struct {
   m_uint64_t mask;
   m_uint64_t hi;
   m_uint64_t lo0;
   m_uint64_t lo1;
}tlb_entry_t;

/* System Coprocessor (CP0) definition */
typedef struct {
   m_uint64_t reg[MIPS64_CP0_REG_NR];
   tlb_entry_t tlb[MIPS64_TLB_MAX_ENTRIES];
   
   /* Number of TLB entries */
   u_int tlb_entries;

   /* Extensions for R7000 CP0 Set1 */
   m_uint32_t ipl_lo,ipl_hi,int_ctl;
   m_uint32_t derraddr0,derraddr1;
}mips_cp0_t;

/* FPU Coprocessor (CP1) definition */
typedef struct {
   m_uint64_t reg[MIPS64_CP1_REG_NR];
}mips_cp1_t;

/* MIPS CPU definition */
struct cpu_mips {
   /* MTS32/MTS64 caches */
   union {
      mts32_entry_t *mts32_cache;
      mts64_entry_t *mts64_cache;
   }mts_u;

   /* Virtual version of CP0 Compare Register */
   m_uint32_t cp0_virt_cnt_reg,cp0_virt_cmp_reg;

   /* General Purpose Registers, Pointer Counter, LO/HI, IRQ */
   m_uint32_t irq_pending,irq_cause,ll_bit;
   m_uint64_t pc,gpr[MIPS64_GPR_NR];
   m_uint64_t lo,hi,ret_pc;
   
   /* Code page translation cache */
   mips64_jit_tcb_t **exec_blk_map;

   /* Virtual address to physical page translation */
   fastcall int (*translate)(cpu_mips_t *cpu,m_uint64_t vaddr,
                             m_uint32_t *phys_page);

   /* Memory access functions */
   mips_memop_fn mem_op_fn[MIPS_MEMOP_MAX];

   /* Memory lookup function (to load ELF image,...) */
   void *(*mem_op_lookup)(cpu_mips_t *cpu,m_uint64_t vaddr);

   /* System coprocessor (CP0) */
   mips_cp0_t cp0;
   
   /* FPU (CP1) */
   mips_cp1_t fpu;

   /* Address bus mask for physical addresses */
   m_uint64_t addr_bus_mask;

   /* IRQ counters and cause */
   m_uint64_t irq_count,timer_irq_count,irq_fp_count;
   pthread_mutex_t irq_lock;

   /* Current and free lists of translated code blocks */
   mips64_jit_tcb_t *tcb_list,*tcb_last,*tcb_free_list;

   /* Executable page area */
   void *exec_page_area;
   size_t exec_page_area_size;
   size_t exec_page_count,exec_page_alloc;
   insn_exec_page_t *exec_page_free_list;
   insn_exec_page_t *exec_page_array;

   /* Idle PC value */
   volatile m_uint64_t idle_pc;

   /* Timer IRQs */
   volatile u_int timer_irq_pending;
   u_int timer_irq_freq;
   u_int timer_irq_check_itv;
   u_int timer_drift;

   /* IRQ disable flag */
   volatile u_int irq_disable;

   /* IRQ idling preemption */
   u_int irq_idle_preempt[8];

   /* Generic CPU instance pointer */
   cpu_gen_t *gen;

   /* VM instance */
   vm_instance_t *vm;

   /* non-JIT mode instruction counter */
   m_uint64_t insn_exec_count;

   /* MTS map/unmap/rebuild operations */
   void (*mts_map)(cpu_mips_t *cpu,m_uint64_t vaddr,
                   m_uint64_t paddr,m_uint32_t len,
                   int cache_access,int tlb_index);

   void (*mts_unmap)(cpu_mips_t *cpu,m_uint64_t vaddr,m_uint32_t len,
                     m_uint32_t val,int tlb_index);

   void (*mts_shutdown)(cpu_mips_t *cpu);

   /* MTS cache statistics */
   m_uint64_t mts_misses,mts_lookups;

   /* JIT flush method */
   u_int jit_flush_method;

   /* Number of compiled pages */
   u_int compiled_pages;

   /* Fast memory operations use */
   u_int fast_memop;

   /* Direct block jump */
   u_int exec_blk_direct_jump;

   /* Address mode (32 or 64 bits) */
   u_int addr_mode;

   /* Current exec page (non-JIT) info */
   m_uint64_t njm_exec_page;
   mips_insn_t *njm_exec_ptr;

   /* Performance counter (number of instructions executed by CPU) */
   m_uint32_t perf_counter;

   /* Breakpoints */
   m_uint64_t breakpoints[MIPS64_MAX_BREAKPOINTS];
   u_int breakpoints_enabled;

   /* Symtrace */
   int sym_trace;
   rbtree_tree *sym_tree;
};

#define MIPS64_IRQ_LOCK(cpu)   pthread_mutex_lock(&(cpu)->irq_lock)
#define MIPS64_IRQ_UNLOCK(cpu) pthread_mutex_unlock(&(cpu)->irq_lock)

/* Register names */
extern char *mips64_gpr_reg_names[];

/* Get cacheability info */
int mips64_cca_cached(m_uint8_t val);

/* Reset a MIPS64 CPU */
int mips64_reset(cpu_mips_t *cpu);

/* Initialize a MIPS64 processor */
int mips64_init(cpu_mips_t *cpu);

/* Delete a MIPS64 processor */
void mips64_delete(cpu_mips_t *cpu);

/* Set the CPU PRID register */
void mips64_set_prid(cpu_mips_t *cpu,m_uint32_t prid);

/* Set idle PC value */
void mips64_set_idle_pc(cpu_gen_t *cpu,m_uint64_t addr);

/* Timer IRQ */
void *mips64_timer_irq_run(cpu_mips_t *cpu);

/* Determine an "idling" PC */
int mips64_get_idling_pc(cpu_gen_t *cpu);

/* Set an IRQ (VM IRQ standard routing) */
void mips64_vm_set_irq(vm_instance_t *vm,u_int irq);

/* Clear an IRQ (VM IRQ standard routing) */
void mips64_vm_clear_irq(vm_instance_t *vm,u_int irq);

/* Update the IRQ flag */
void mips64_update_irq_flag(cpu_mips_t *cpu);

/* Generate an exception */
void mips64_trigger_exception(cpu_mips_t *cpu,u_int exc_code,int bd_slot);

/*
 * Increment count register and trigger the timer IRQ if value in compare 
 * register is the same.
 */
fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu);

/* Trigger the Timer IRQ */
fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu);

/* Execute ERET instruction */
fastcall void mips64_exec_eret(cpu_mips_t *cpu);

/* Execute SYSCALL instruction */
fastcall void mips64_exec_syscall(cpu_mips_t *cpu);

/* Execute BREAK instruction */
fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code);

/* Trigger a Trap Exception */
fastcall void mips64_trigger_trap_exception(cpu_mips_t *cpu);

/* Trigger IRQs */
fastcall void mips64_trigger_irq(cpu_mips_t *cpu);

/* Set an IRQ */
void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq);

/* Clear an IRQ */
void mips64_clear_irq(cpu_mips_t *cpu,m_uint8_t irq);

/* DMFC1 */
fastcall void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);

/* DMTC1 */
fastcall void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);

/* MFC1 */
fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);

/* MTC1 */
fastcall void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg);

/* Virtual breakpoint */
fastcall void mips64_run_breakpoint(cpu_mips_t *cpu);

/* Add a virtual breakpoint */
int mips64_add_breakpoint(cpu_gen_t *cpu,m_uint64_t pc);

/* Remove a virtual breakpoint */
void mips64_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t pc);

/* Debugging for register-jump to address 0 */
fastcall void mips64_debug_jr0(cpu_mips_t *cpu);

/* Set a register */
void mips64_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val);

/* Dump registers of a MIPS64 processor */
void mips64_dump_regs(cpu_gen_t *cpu);

/* Dump a memory block */
void mips64_dump_memory(cpu_mips_t *cpu,m_uint64_t vaddr,u_int count);

/* Dump the stack */
void mips64_dump_stack(cpu_mips_t *cpu,u_int count);

/* Save the CPU state into a file */
int mips64_save_state(cpu_mips_t *cpu,char *filename);

/* Load a raw image into the simulated memory */
int mips64_load_raw_image(cpu_mips_t *cpu,char *filename,m_uint64_t vaddr);

/* Load an ELF image into the simulated memory */
int mips64_load_elf_image(cpu_mips_t *cpu,char *filename,int skip_load,
                          m_uint32_t *entry_point);

/* Symbol lookup */
struct symbol *mips64_sym_lookup(cpu_mips_t *cpu,m_uint64_t addr);

/* Insert a new symbol */
struct symbol *mips64_sym_insert(cpu_mips_t *cpu,char *name,m_uint64_t addr);

/* Create the symbol tree */
int mips64_sym_create_tree(cpu_mips_t *cpu);

/* Load a symbol file */
int mips64_sym_load_file(cpu_mips_t *cpu,char *filename);

#endif