ppc32.h

思科路由器仿真器,用来仿7200系列得,可以在电脑上模拟路由器

/* FPU Coprocessor definition */
typedef struct {
   m_uint64_t reg[PPC32_FPU_REG_NR];
}ppc_fpu_t;

/* Maximum number of breakpoints */
#define PPC32_MAX_BREAKPOINTS  8

/* zzz */
struct ppc32_vtlb_entry {
   m_uint32_t vaddr;
   m_uint32_t haddr;
};

/* PowerPC CPU definition */
struct cpu_ppc {
   /* Instruction address */
   m_uint32_t ia;

   /* General Purpose registers */
   m_uint32_t gpr[PPC32_GPR_NR];

   struct ppc32_vtlb_entry vtlb[PPC32_GPR_NR];

   /* Pending IRQ */
   volatile m_uint32_t irq_pending,irq_check;

   /* XER, Condition Register, Link Register, Count Register */
   m_uint32_t xer,lr,ctr,reserve;
   m_uint32_t xer_ca;

   /* Condition Register (CR) fields */
   u_int cr_fields[8];

   /* MTS caches (Instruction+Data) */
   mts32_entry_t *mts_cache[2];

   /* Code page translation cache and physical page mapping */
   ppc32_jit_tcb_t **exec_blk_map,**exec_phys_map;

   /* Virtual address to physical page translation */
   fastcall int (*translate)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid,
                             m_uint32_t *phys_page);

   /* Memory access functions */
   ppc_memop_fn mem_op_fn[PPC_MEMOP_MAX];

   /* Memory lookup function (to load ELF image,...) */
   void *(*mem_op_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int cid);

   /* MTS slow lookup function */
   mts32_entry_t *(*mts_slow_lookup)(cpu_ppc_t *cpu,m_uint32_t vaddr,
                                     u_int cid,u_int op_code,u_int op_size,
                                     u_int op_type,m_uint64_t *data,
                                     mts32_entry_t *alt_entry);

   /* IRQ counters */
   m_uint64_t irq_count,timer_irq_count,irq_fp_count;
   pthread_mutex_t irq_lock;

   /* Current and free lists of translated code blocks */
   ppc32_jit_tcb_t *tcb_list,*tcb_last,*tcb_free_list;

   /* Executable page area */
   void *exec_page_area;
   size_t exec_page_area_size;
   size_t exec_page_count,exec_page_alloc;
   insn_exec_page_t *exec_page_free_list;
   insn_exec_page_t *exec_page_array;

   /* Idle PC value */
   volatile m_uint32_t idle_pc;

   /* Timer IRQs */
   volatile u_int timer_irq_pending,timer_irq_armed;
   u_int timer_irq_freq;
   u_int timer_irq_check_itv;
   u_int timer_drift;

   /* IRQ disable flag */
   volatile u_int irq_disable;

   /* IBAT (Instruction) and DBAT (Data) registers */
   struct ppc32_bat_reg bat[2][PPC32_BAT_NR];
   
   /* Segment registers */
   m_uint32_t sr[PPC32_SR_NR];

   /* Page Table Address */
   m_uint32_t sdr1;
   void *sdr1_hptr;

   /* MSR (Machine state register) */
   m_uint32_t msr;

   /* Interrupt Registers (SRR0/SRR1) */
   m_uint32_t srr0,srr1,dsisr,dar;

   /* SPRG registers */
   m_uint32_t sprg[4];

   /* PVR (Processor Version Register) */
   m_uint32_t pvr;

   /* Time-Base register */
   m_uint64_t tb;

   /* Decrementer */
   m_uint32_t dec;

   /* Hardware Implementation Dependent Registers */
   m_uint32_t hid0,hid1;

   /* String instruction position (lswi/stswi) */
   u_int sw_pos;

   /* PowerPC 405 TLB */
   struct ppc405_tlb_entry ppc405_tlb[PPC405_TLB_ENTRIES];
   m_uint32_t ppc405_pid;

   /* MPC860 IMMR register */
   m_uint32_t mpc860_immr;

   /* FPU */
   ppc_fpu_t fpu;

   /* Generic CPU instance pointer */
   cpu_gen_t *gen;

   /* VM instance */
   vm_instance_t *vm;
   
   /* MTS cache statistics */
   m_uint64_t mts_misses,mts_lookups;

   /* JIT flush method */
   u_int jit_flush_method;

   /* Number of compiled pages */
   u_int compiled_pages;

   /* Fast memory operations use */
   u_int fast_memop;

   /* Direct block jump */
   u_int exec_blk_direct_jump;

   /* Current exec page (non-JIT) info */
   m_uint64_t njm_exec_page;
   mips_insn_t *njm_exec_ptr;

   /* Performance counter (non-JIT) */
   m_uint32_t perf_counter;

   /* non-JIT mode instruction counter */
   m_uint64_t insn_exec_count;

   /* Breakpoints */
   m_uint32_t breakpoints[PPC32_MAX_BREAKPOINTS];
   u_int breakpoints_enabled;

   /* JIT host register allocation */
   char *jit_hreg_seq_name;
   int ppc_reg_map[PPC32_GPR_NR];
   struct hreg_map *hreg_map_list,*hreg_lru;
   struct hreg_map hreg_map[JIT_HOST_NREG];
};

#define PPC32_CR_FIELD_OFFSET(f) \
   (OFFSET(cpu_ppc_t,cr_fields)+((f) * sizeof(u_int)))

/* Get the full CR register */
static forced_inline m_uint32_t ppc32_get_cr(cpu_ppc_t *cpu)
{
   m_uint32_t cr = 0;
   int i;

   for(i=0;i<8;i++)
      cr |= cpu->cr_fields[i] << (28 - (i << 2));

   return(cr);
}

/* Set the CR fields given a CR value */
static forced_inline void ppc32_set_cr(cpu_ppc_t *cpu,m_uint32_t cr)
{
   int i;

   for(i=0;i<8;i++)
      cpu->cr_fields[i] = (cr >> (28 - (i << 2))) & 0x0F;
}

/* Get a CR bit */
static forced_inline m_uint32_t ppc32_read_cr_bit(cpu_ppc_t *cpu,u_int bit)
{
   m_uint32_t res;

   res = cpu->cr_fields[ppc32_get_cr_field(bit)] >> ppc32_get_cr_bit(bit);
   return(res & 0x01);
}

/* Set a CR bit */
static forced_inline void ppc32_set_cr_bit(cpu_ppc_t *cpu,u_int bit)
{
   cpu->cr_fields[ppc32_get_cr_field(bit)] |= 1 << ppc32_get_cr_bit(bit);
}

/* Clear a CR bit */
static forced_inline void ppc32_clear_cr_bit(cpu_ppc_t *cpu,u_int bit)
{
   cpu->cr_fields[ppc32_get_cr_field(bit)] &= ~(1 << ppc32_get_cr_bit(bit));
}

/* Reset a PowerPC CPU */
int ppc32_reset(cpu_ppc_t *cpu);

/* Initialize a PowerPC processor */
int ppc32_init(cpu_ppc_t *cpu);

/* Delete a PowerPC processor */
void ppc32_delete(cpu_ppc_t *cpu);

/* Set the processor version register (PVR) */
void ppc32_set_pvr(cpu_ppc_t *cpu,m_uint32_t pvr);

/* Set idle PC value */
void ppc32_set_idle_pc(cpu_gen_t *cpu,m_uint64_t addr);

/* Timer IRQ */
void *ppc32_timer_irq_run(cpu_ppc_t *cpu);

/* Determine an "idling" PC */
int ppc32_get_idling_pc(cpu_gen_t *cpu);

/* Generate an exception */
void ppc32_trigger_exception(cpu_ppc_t *cpu,u_int exc_vector);

/* Trigger the decrementer exception */
void ppc32_trigger_timer_irq(cpu_ppc_t *cpu);

/* Trigger IRQs */
fastcall void ppc32_trigger_irq(cpu_ppc_t *cpu);

/* Virtual breakpoint */
fastcall void ppc32_run_breakpoint(cpu_ppc_t *cpu);

/* Add a virtual breakpoint */
int ppc32_add_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);

/* Remove a virtual breakpoint */
void ppc32_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t ia);

/* Set a register */
void ppc32_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val);

/* Dump registers of a PowerPC processor */
void ppc32_dump_regs(cpu_gen_t *cpu);

/* Dump MMU registers */
void ppc32_dump_mmu(cpu_gen_t *cpu);

/* Load a raw image into the simulated memory */
int ppc32_load_raw_image(cpu_ppc_t *cpu,char *filename,m_uint32_t vaddr);

/* Load an ELF image into the simulated memory */
int ppc32_load_elf_image(cpu_ppc_t *cpu,char *filename,int skip_load,
                         m_uint32_t *entry_point);

/* Run PowerPC code in step-by-step mode */
void *ppc32_exec_run_cpu(cpu_gen_t *gen);

#endif