reg.vhd.txt

lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器

-------------------------------------------------------------------------------
--
-- Universitaet Heidelberg
-- Kirchhoff-Institut fuer Physik
-- Lehrstuhl fuer Technische Informatik
--
-- Filename:      reg.vhd
-- Author:        Jan de Cuveland
-- Description:   FF-based Register of variable width
-- Comment:       
--
-- Version history:
-------------------------------------------------------------------------------
-- Version  | Author      | Date     | Modification
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--  1.0     | de Cuveland | 28.09.00 |  created
-------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;  
USE IEEE.std_logic_signed.ALL;

-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity reg is
	generic ( WIDTH	: integer := 1 );
	port (	D	: in  std_logic_vector(WIDTH-1 downto 0);
		Q	: out std_logic_vector(WIDTH-1 downto 0);
		clk	: in  std_logic;
		reset_n	: in  std_logic	);
end reg;

-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture behavioral of reg is

begin

BitFlop: process (reset_n, clk)
begin
	if (reset_n = '0') then
		Q <= (q'range => '0');
	elsif (clk'event and clk = '1') then
		Q <= D;
	end if;
end process;

end behavioral;

-------------------------------------------------------------------------------
-- CONFIGURATION
-------------------------------------------------------------------------------
-- synopsys translate_off

configuration reg_CFG of reg is
	for behavioral
	end for;
end reg_CFG;

-- synopsys translate_on