orn.vhd.txt

lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器

-------------------------------------------------------------------------------
--
-- Universitaet Heidelberg
-- Kirchhoff-Institut fuer Physik
-- Lehrstuhl fuer Technische Informatik
--
-- Filename:      orn.vhd
-- Author:        Jan de Cuveland
-- Description:   Logic Gate: Q = A OR NOT B
-- Comment:       
--
-- Version history:
-------------------------------------------------------------------------------
-- Version  | Author      | Date     | Modification
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--  1.0     | de Cuveland | 28.09.00 |  created
-------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;  
USE IEEE.std_logic_signed.ALL;

-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity orn is
	port (	A, B	: in  std_logic;
		Q	: out std_logic );
end orn;

-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture behavioral of orn is

begin

Q <= A or not B;

end behavioral;

-------------------------------------------------------------------------------
-- CONFIGURATION
-------------------------------------------------------------------------------
-- synopsys translate_off

configuration orn_CFG of orn is
	for behavioral
	end for;
end orn_CFG;

-- synopsys translate_on