array_divider.vhd.txt

lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器

-------------------------------------------------------------------------------
--
-- Universitaet Heidelberg
-- Kirchhoff-Institut fuer Physik
-- Lehrstuhl fuer Technische Informatik
--
-- Filename:      array_divider.vhd
-- Author:        Jan de Cuveland
-- Description:   Simple array divider based on controlled add/subtract cells
-- Comment:       16/8/8 bit, unsigned divider module
--
-- Version history:
-------------------------------------------------------------------------------
-- Version  | Author      | Date     | Modification
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--  1.0     | de Cuveland | 25.08.00 |  created
-------------------------------------------------------------------------------
--  1.1     | de Cuveland | 19.10.00 |  generic PIPELINED added and implemented
-------------------------------------------------------------------------------
--  1.2     | de Cuveland | 23.10.00 |  implementation of pipeline completed
-------------------------------------------------------------------------------
--  1.3     | de Cuveland | 31.10.00 |  added "separate bl" mode
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;

-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity array_divider is
  generic ( WIDTH     : integer := 8;
            USE_BLS   : integer := 1;    -- 0=none, 1=simple bls, 2=separate
            PIPELINED : integer := 1 );  -- only implemented for WIDTH=8
  -- bls: full borrow lookahead subtractor
  port ( z       : in  std_logic_vector(2*WIDTH-1 downto 0);
         d       : in  std_logic_vector(WIDTH-1 downto 0);
         q       : out std_logic_vector(WIDTH-1 downto 0);
         e       : out std_logic;
         clk     : in  std_logic;
         reset_n : in  std_logic );
end array_divider;

-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture behavioral of array_divider is

-- Controlled Subtractor Cell
  component cs_cell
    generic ( USE_CO : integer := 1 );
    port ( a, b, e, ci : in  std_logic;
           co, s       : out std_logic );
  end component;

-- Borrow Lookahead Generator
  component blg
    generic ( WIDTH    : integer := 4;
              CIN_USED : integer := 0 );
    port ( A, B : in  std_logic_vector(WIDTH-1 downto 0);
           CIN  : in  std_logic;
           C    : out std_logic_vector(WIDTH downto 1) );
  end component;

-- FF-based Register
  component reg
    generic ( WIDTH : integer := 1 );
    port ( D       : in  std_logic_vector(WIDTH-1 downto 0);
           Q       : out std_logic_vector(WIDTH-1 downto 0);
           clk     : in  std_logic;
           reset_n : in  std_logic );
  end component;

-- Gate: or-not
  component orn
    port ( A, B : in  std_logic;
           Q    : out std_logic );
  end component;

  signal q_full : std_logic_vector(2*WIDTH-1 downto 0);
  signal z_reg  : std_logic_vector(2*WIDTH-1 downto 0);
  signal d_reg  : std_logic_vector(WIDTH-1 downto 0);
  signal q_temp : std_logic_vector(WIDTH-1 downto 0);
  signal e_temp : std_logic;

  signal s : std_logic_vector(WIDTH-1 downto 0);  -- Divisionsrest

  type s_type is array (WIDTH downto 0) of
    std_logic_vector(WIDTH downto 0);
  type c_type is array (WIDTH-1 downto 0) of
    std_logic_vector(WIDTH downto 0);
  type d_type is array (WIDTH-1 downto 0) of
    std_logic_vector(WIDTH-1 downto 0);
  type e_type is array (WIDTH-1 downto 0) of
    std_logic;
  type z_type is array (WIDTH-1 downto 0) of
    std_logic_vector(WIDTH-1 downto 0);
  type ct_sub_type is array (WIDTH downto 1) of
    std_logic_vector(WIDTH downto 1);
  type ct_type is array (WIDTH-1 downto 0) of
    ct_sub_type;
  
  signal a, s_out : s_type;
  signal c_all    : c_type;
  signal d_all    : d_type;
  signal e_all    : e_type;
  signal z_all    : z_type;
  signal ct       : ct_type;

  signal e_temp_vec : std_logic_vector(0 downto 0);
  signal e_vec      : std_logic_vector(0 downto 0);

  signal const_0 : std_logic;

begin

  const_0 <= '0';

  REG_Z : reg
    generic map ( WIDTH => 2*WIDTH )
    port map ( D       => z,
               Q       => z_reg,
               clk     => clk,
               reset_n => reset_n );

  REG_D : reg
    generic map ( WIDTH => WIDTH )
    port map ( D       => d,
               Q       => d_reg,
               clk     => clk,
               reset_n => reset_n );

  REG_Q : reg
    generic map ( WIDTH => WIDTH )
    port map ( D       => q_temp,
               Q       => q,
               clk     => clk,
               reset_n => reset_n );

  REG_E : reg
    generic map ( WIDTH => 1 )
    port map ( D       => e_temp_vec,
               Q       => e_vec,
               clk     => clk,
               reset_n => reset_n );

  e_temp_vec(0)  <= e_temp;
  e              <= e_vec(0);
  z_all(WIDTH-1) <= z_reg(WIDTH-1 downto 0);
  d_all(WIDTH-1) <= d_reg;

  WITHOUT_BL : if (USE_BLS = 0) generate
    GEN1 : for i in WIDTH-1 downto 0 generate
      DIV2 : for j in WIDTH-1 downto 0 generate
        DIV_CELL : cs_cell
          generic map ( USE_CO => 1 )
          port map ( a  => a(i+1)(j), b => d_all(i)(j),
                     e  => e_all(i),
                     ci => c_all(i)(j), co => c_all(i)(j+1),
                     s  => s_out(i)(j+1) );
      end generate;
    end generate;

    GEN2 : for i in WIDTH-1 downto 0 generate
      GEN2A : orn
        port map ( A => a(i+1)(WIDTH), B => c_all(i)(WIDTH),
                   Q => e_all(i) );
      c_all(i)(0)   <= '0';
      q_temp(i)     <= e_all(i);
      s_out(i+1)(0) <= z_all(i)(i);
    end generate;
  end generate;

  WITH_BL : if not (USE_BLS = 0) generate
    GEN1 : for i in WIDTH-1 downto 0 generate
      DIV2 : for j in WIDTH-1 downto 0 generate
        DIV_CELL : cs_cell
          generic map ( USE_CO => 0 )
          port map ( a  => a(i+1)(j), b => d_all(i)(j),
                     e  => e_all(i),
                     ci => c_all(i)(j), co => open,
                     s  => s_out(i)(j+1) );
      end generate;
    end generate;

    GEN2 : for i in WIDTH-1 downto 0 generate
      NORMAL_BL : if not (USE_BLS = 2) generate
        BL1 : blg
          generic map ( WIDTH => WIDTH, CIN_USED => 0 )
          port map ( A   => a(i+1)(WIDTH-1 downto 0),
                     B   => d_all(i),
                     CIN => const_0,
                     C   => c_all(i)(WIDTH downto 1));      
      end generate NORMAL_BL;
      SEPARATE_BL : if (USE_BLS = 2) generate
        SEP_BL : for j in WIDTH downto 1 generate
          BL1 : blg
            generic map ( WIDTH => WIDTH, CIN_USED => 0 )
            port map ( A   => a(i+1)(WIDTH-1 downto 0),
                       B   => d_all(i),
                       CIN => const_0,
                       C   => ct(i)(j));
          c_all(i)(j) <= ct(i)(j)(j);
        end generate SEP_BL;
      end generate SEPARATE_BL;
      GEN2A : orn
        port map ( A => a(i+1)(WIDTH),
                   B => c_all(i)(WIDTH),
                   Q => e_all(i) );
      c_all(i)(0)   <= '0';
      q_temp(i)     <= e_all(i);
      s_out(i+1)(0) <= z_all(i)(i);
    end generate;
  end generate;

  WITHOUT_PIPELINE : if (PIPELINED = 0) or not (WIDTH = 8) generate
    S_CONNECT : for i in WIDTH downto 0 generate
      a(i) <= s_out(i);
    end generate S_CONNECT;
    DZ_CONNECT : for i in WIDTH-2 downto 0 generate
      d_all(i) <= d_all(WIDTH-1);
      z_all(i) <= z_all(WIDTH-1);
    end generate DZ_CONNECT;
  end generate;

  WITH_PINELINE : if not (PIPELINED = 0) and (WIDTH = 8) generate
    -- Nur fuer WIDTH = 8! (simulation ok)
    
    a(8) <= s_out(8);
    a(7) <= s_out(7);
    a(6) <= s_out(6);
    -- a(5) <= s_out(5);
    reg_1 : reg
      generic map (
        WIDTH => WIDTH+1)
      port map (
        D       => s_out(5),
        Q       => a(5),
        clk     => clk,
        reset_n => reset_n);
    a(4) <= s_out(4);
    a(3) <= s_out(3);
    -- a(2) <= s_out(2);
    reg_2 : reg
      generic map (
        WIDTH => WIDTH+1)
      port map (
        D       => s_out(2),
        Q       => a(2),
        clk     => clk,
        reset_n => reset_n);
    a(1) <= s_out(1);
    a(0) <= s_out(0);

    d_all(6) <= d_all(7);
    d_all(5) <= d_all(6);
    reg_3 : reg
      generic map (
        WIDTH => WIDTH)
      port map (
        D       => d_all(5),
        Q       => d_all(4),
        clk     => clk,
        reset_n => reset_n);
    d_all(3) <= d_all(4);
    d_all(2) <= d_all(3);
    reg_4 : reg
      generic map (
        WIDTH => WIDTH)
      port map (
        D       => d_all(2),
        Q       => d_all(1),
        clk     => clk,
        reset_n => reset_n);
    d_all(0) <= d_all(1);

    z_all(6) <= z_all(7);
    z_all(5) <= z_all(6);
    reg_5 : reg
      generic map (
        WIDTH => 5)
      port map (
        D       => z_all(5)(4 downto 0),
        Q       => z_all(4)(4 downto 0),
        clk     => clk,
        reset_n => reset_n);
    z_all(3) <= z_all(4);
    z_all(2) <= z_all(3);
    reg_6 : reg
      generic map (
        WIDTH => 2)
      port map (
        D       => z_all(2)(1 downto 0),
        Q       => z_all(1)(1 downto 0),
        clk     => clk,
        reset_n => reset_n);
    z_all(0) <= z_all(1);
  end generate;

  GEN3 : for j in WIDTH-1 downto 0 generate
    s(j)              <= a(0)(j);
    s_out(WIDTH)(j+1) <= z_reg(j+WIDTH);
  end generate;
  
end behavioral;

-------------------------------------------------------------------------------
-- CONFIGURATION
-------------------------------------------------------------------------------
-- synopsys translate_off

configuration array_divider_CFG of array_divider is
  for behavioral
  end for;
end array_divider_CFG;

-- synopsys translate_on