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📄 main.lss

📁 adhoc汇聚节点程序源代码(点对多点)——for atmega128
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     5be:	11 24       	eor	r1, r1
     5c0:	0f 93       	push	r16
     5c2:	1f 93       	push	r17
     5c4:	2f 93       	push	r18
     5c6:	3f 93       	push	r19
     5c8:	4f 93       	push	r20
     5ca:	5f 93       	push	r21
     5cc:	6f 93       	push	r22
     5ce:	7f 93       	push	r23
     5d0:	8f 93       	push	r24
     5d2:	9f 93       	push	r25
     5d4:	af 93       	push	r26
     5d6:	bf 93       	push	r27
     5d8:	ef 93       	push	r30
     5da:	ff 93       	push	r31
     5dc:	04 b1       	in	r16, 0x04	; 4
     5de:	15 b1       	in	r17, 0x05	; 5
     5e0:	13 70       	andi	r17, 0x03	; 3
     5e2:	34 9a       	sbi	0x06, 4	; 6
     5e4:	37 98       	cbi	0x06, 7	; 6
     5e6:	0e 94 93 08 	call	0x1126
     5ea:	c8 01       	movw	r24, r16
     5ec:	0e 94 fb 01 	call	0x3f6
     5f0:	ff 91       	pop	r31
     5f2:	ef 91       	pop	r30
     5f4:	bf 91       	pop	r27
     5f6:	af 91       	pop	r26
     5f8:	9f 91       	pop	r25
     5fa:	8f 91       	pop	r24
     5fc:	7f 91       	pop	r23
     5fe:	6f 91       	pop	r22
     600:	5f 91       	pop	r21
     602:	4f 91       	pop	r20
     604:	3f 91       	pop	r19
     606:	2f 91       	pop	r18
     608:	1f 91       	pop	r17
     60a:	0f 91       	pop	r16
     60c:	0f 90       	pop	r0
     60e:	0f be       	out	0x3f, r0	; 63
     610:	0f 90       	pop	r0
     612:	1f 90       	pop	r1
     614:	18 95       	reti

00000616 <CC1000ControlGetLOStatus>:


bool CC1000ControlGetLOStatus(void)							// 得到CC1000的LO状态
{
	return CC1000ControlM_gCurrentParameters[0x1e];
     616:	80 91 ea 01 	lds	r24, 0x01EA
}
     61a:	99 27       	eor	r25, r25
     61c:	08 95       	ret

0000061e <CC1000ControlComputeFreq>:

result_t CC1000ControlSelectLock(uint8_t Value)				// 设置CC1000的PLL
{
	CC1000ControlM_gCurrentParameters[0xd] = Value << 4;
	return CC1000HPLWrite(0x0D, Value << 4);
}

result_t CC1000ControlChipconCal(void)
{
	CC1000HPLWrite(0x0B, 0x00);
	CC1000HPLWrite(0x42, 0x3f);
	
	CC1000HPLWrite(0x00, (
		1 << 4) | (1 << 0));
	
	CC1000HPLWrite(0x0E, ((
		1 << 7) | (
		1 << 5)) | (6 << 0));
	
	while ((CC1000HPLRead(0x0E) & (1 << 3)) == 0) ;
	
	CC1000HPLWrite(0x0E, (
		1 << 5) | (6 << 0));
	
	CC1000HPLWrite(0x00, (((
		1 << 7) | (1 << 6)) | (1 << 5)) | (
		1 << 0));
	
	CC1000HPLWrite(0x09, CC1000ControlM_gCurrentParameters[29]);
	CC1000HPLWrite(0x0B, 0x00);
	
	CC1000HPLWrite(0x0E, ((
		1 << 7) | (
		1 << 5)) | (6 << 0));
	
	while ((CC1000HPLRead(0x0E) & (1 << 3)) == 0) ;
	
	CC1000HPLWrite(0x0E, (
		1 << 5) | (6 << 0));
	
	return SUCCESS;
}

void CC1000ControlCC1000SetFreq(void)
{
	uint8_t i;
	
	for (i = 1; i < 0x0d; i++) {
		CC1000HPLWrite(i, CC1000ControlM_gCurrentParameters[i]);
    }
	
	
	CC1000HPLWrite(0x12, CC1000ControlM_gCurrentParameters[0x12]);
	
	CC1000ControlChipconCal();
	
	return;
}

uint32_t CC1000ControlComputeFreq(uint32_t desiredFreq)
{
     61e:	2f 92       	push	r2
     620:	3f 92       	push	r3
     622:	4f 92       	push	r4
     624:	5f 92       	push	r5
     626:	6f 92       	push	r6
     628:	7f 92       	push	r7
     62a:	8f 92       	push	r8
     62c:	9f 92       	push	r9
     62e:	af 92       	push	r10
     630:	bf 92       	push	r11
     632:	cf 92       	push	r12
     634:	df 92       	push	r13
     636:	ef 92       	push	r14
     638:	ff 92       	push	r15
     63a:	0f 93       	push	r16
     63c:	1f 93       	push	r17
     63e:	cf 93       	push	r28
     640:	df 93       	push	r29
     642:	cd b7       	in	r28, 0x3d	; 61
     644:	de b7       	in	r29, 0x3e	; 62
     646:	6e 97       	sbiw	r28, 0x1e	; 30
     648:	0f b6       	in	r0, 0x3f	; 63
     64a:	f8 94       	cli
     64c:	de bf       	out	0x3e, r29	; 62
     64e:	0f be       	out	0x3f, r0	; 63
     650:	cd bf       	out	0x3d, r28	; 61
     652:	69 83       	std	Y+1, r22	; 0x01
     654:	7a 83       	std	Y+2, r23	; 0x02
     656:	8b 83       	std	Y+3, r24	; 0x03
     658:	9c 83       	std	Y+4, r25	; 0x04
  uint32_t ActualChannel = 0;
     65a:	1d 82       	std	Y+5, r1	; 0x05
     65c:	1e 82       	std	Y+6, r1	; 0x06
     65e:	1f 82       	std	Y+7, r1	; 0x07
     660:	18 86       	std	Y+8, r1	; 0x08
  uint32_t RXFreq = 0;
     662:	20 e0       	ldi	r18, 0x00	; 0
     664:	30 e0       	ldi	r19, 0x00	; 0
     666:	40 e0       	ldi	r20, 0x00	; 0
     668:	50 e0       	ldi	r21, 0x00	; 0
     66a:	29 87       	std	Y+9, r18	; 0x09
     66c:	3a 87       	std	Y+10, r19	; 0x0a
     66e:	4b 87       	std	Y+11, r20	; 0x0b
     670:	5c 87       	std	Y+12, r21	; 0x0c
  uint32_t TXFreq = 0;
     672:	2d 87       	std	Y+13, r18	; 0x0d
     674:	3e 87       	std	Y+14, r19	; 0x0e
     676:	4f 87       	std	Y+15, r20	; 0x0f
     678:	58 8b       	std	Y+16, r21	; 0x10
  int32_t Offset = 0x7fffffff;
     67a:	2f ef       	ldi	r18, 0xFF	; 255
     67c:	3f ef       	ldi	r19, 0xFF	; 255
     67e:	4f ef       	ldi	r20, 0xFF	; 255
     680:	5f e7       	ldi	r21, 0x7F	; 127
     682:	29 8b       	std	Y+17, r18	; 0x11
     684:	3a 8b       	std	Y+18, r19	; 0x12
     686:	4b 8b       	std	Y+19, r20	; 0x13
     688:	5c 8b       	std	Y+20, r21	; 0x14
  uint16_t FSep = 0;
     68a:	1d 8e       	std	Y+29, r1	; 0x1d
     68c:	1e 8e       	std	Y+30, r1	; 0x1e
  uint8_t RefDiv = 0;
     68e:	1d 8a       	std	Y+21, r1	; 0x15
  uint8_t i;

  for (i = 0; i < 9; i++) {
     690:	3d 89       	ldd	r19, Y+21	; 0x15
     692:	3e 8b       	std	Y+22, r19	; 0x16
     694:	44 e2       	ldi	r20, 0x24	; 36
     696:	51 e0       	ldi	r21, 0x01	; 1
     698:	4f 8b       	std	Y+23, r20	; 0x17
     69a:	58 8f       	std	Y+24, r21	; 0x18
     69c:	82 e1       	ldi	r24, 0x12	; 18
     69e:	91 e0       	ldi	r25, 0x01	; 1
     6a0:	89 8f       	std	Y+25, r24	; 0x19
     6a2:	9a 8f       	std	Y+26, r25	; 0x1a
     6a4:	a0 e0       	ldi	r26, 0x00	; 0
     6a6:	b0 e0       	ldi	r27, 0x00	; 0
     6a8:	ab 8f       	std	Y+27, r26	; 0x1b
     6aa:	bc 8f       	std	Y+28, r27	; 0x1c

      uint32_t NRef = desiredFreq + CC1000ControlM_IF;
     6ac:	29 81       	ldd	r18, Y+1	; 0x01
     6ae:	3a 81       	ldd	r19, Y+2	; 0x02
     6b0:	4b 81       	ldd	r20, Y+3	; 0x03
     6b2:	5c 81       	ldd	r21, Y+4	; 0x04
     6b4:	20 51       	subi	r18, 0x10	; 16
     6b6:	36 4b       	sbci	r19, 0xB6	; 182
     6b8:	4d 4f       	sbci	r20, 0xFD	; 253
     6ba:	5f 4f       	sbci	r21, 0xFF	; 255
      uint32_t FRef = CC1000ControlM_FRefTbl[i];
     6bc:	ef 89       	ldd	r30, Y+23	; 0x17
     6be:	f8 8d       	ldd	r31, Y+24	; 0x18
     6c0:	a1 90       	ld	r10, Z+
     6c2:	b1 90       	ld	r11, Z+
     6c4:	c1 90       	ld	r12, Z+
     6c6:	d1 90       	ld	r13, Z+
     6c8:	ef 8b       	std	Y+23, r30	; 0x17
     6ca:	f8 8f       	std	Y+24, r31	; 0x18
      uint32_t Channel = 0;
     6cc:	ee 24       	eor	r14, r14
     6ce:	ff 24       	eor	r15, r15
     6d0:	87 01       	movw	r16, r14
      uint32_t RXCalc = 0;
     6d2:	17 01       	movw	r2, r14
     6d4:	28 01       	movw	r4, r16
      uint32_t TXCalc = 0;
      int32_t diff;

      NRef = ((desiredFreq + CC1000ControlM_IF) << 2) / FRef;
     6d6:	72 e0       	ldi	r23, 0x02	; 2
     6d8:	22 0f       	add	r18, r18
     6da:	33 1f       	adc	r19, r19
     6dc:	44 1f       	adc	r20, r20
     6de:	55 1f       	adc	r21, r21
     6e0:	7a 95       	dec	r23
     6e2:	d1 f7       	brne	.-12     	; 0x6d8
     6e4:	ca 01       	movw	r24, r20
     6e6:	b9 01       	movw	r22, r18
     6e8:	a6 01       	movw	r20, r12
     6ea:	95 01       	movw	r18, r10
     6ec:	0e 94 56 0f 	call	0x1eac
      if (NRef & 0x1) {
     6f0:	da 01       	movw	r26, r20
     6f2:	c9 01       	movw	r24, r18
     6f4:	81 70       	andi	r24, 0x01	; 1
     6f6:	90 70       	andi	r25, 0x00	; 0
     6f8:	a0 70       	andi	r26, 0x00	; 0
     6fa:	b0 70       	andi	r27, 0x00	; 0
     6fc:	89 2b       	or	r24, r25
     6fe:	21 f0       	breq	.+8      	; 0x708
          NRef++;
     700:	2f 5f       	subi	r18, 0xFF	; 255
     702:	3f 4f       	sbci	r19, 0xFF	; 255
     704:	4f 4f       	sbci	r20, 0xFF	; 255
     706:	5f 4f       	sbci	r21, 0xFF	; 255
        }

      if (NRef & 0x2) {
     708:	da 01       	movw	r26, r20
     70a:	c9 01       	movw	r24, r18
     70c:	b6 95       	lsr	r27
     70e:	a7 95       	ror	r26
     710:	97 95       	ror	r25
     712:	87 95       	ror	r24
     714:	81 70       	andi	r24, 0x01	; 1
     716:	90 70       	andi	r25, 0x00	; 0
     718:	89 2b       	or	r24, r25
     71a:	59 f0       	breq	.+22     	; 0x732
          RXCalc = 16384 >> 1;
     71c:	21 2c       	mov	r2, r1
     71e:	f0 e2       	ldi	r31, 0x20	; 32
     720:	3f 2e       	mov	r3, r31
     722:	41 2c       	mov	r4, r1
     724:	51 2c       	mov	r5, r1
          Channel = FRef >> 1;
     726:	86 01       	movw	r16, r12
     728:	75 01       	movw	r14, r10
     72a:	16 95       	lsr	r17
     72c:	07 95       	ror	r16
     72e:	f7 94       	ror	r15
     730:	e7 94       	ror	r14
        }

      NRef >>= 2;
     732:	72 e0       	ldi	r23, 0x02	; 2
     734:	56 95       	lsr	r21
     736:	47 95       	ror	r20
     738:	37 95       	ror	r19
     73a:	27 95       	ror	r18
     73c:	7a 95       	dec	r23
     73e:	d1 f7       	brne	.-12     	; 0x734

      RXCalc += NRef * 16384 - 8192;
     740:	da 01       	movw	r26, r20
     742:	c9 01       	movw	r24, r18
     744:	6e e0       	ldi	r22, 0x0E	; 14
     746:	88 0f       	add	r24, r24
     748:	99 1f       	adc	r25, r25
     74a:	aa 1f       	adc	r26, r26
     74c:	bb 1f       	adc	r27, r27
     74e:	6a 95       	dec	r22
     750:	d1 f7       	brne	.-12     	; 0x746
     752:	82 0d       	add	r24, r2
     754:	93 1d       	adc	r25, r3
     756:	a4 1d       	adc	r26, r4
     758:	b5 1d       	adc	r27, r5
     75a:	21 2c       	mov	r2, r1
     75c:	f0 ee       	ldi	r31, 0xE0	; 224
     75e:	3f 2e       	mov	r3, r31
     760:	ff ef       	ldi	r31, 0xFF	; 255
     762:	4f 2e       	mov	r4, r31
     764:	ff ef       	ldi	r31, 0xFF	; 255
     766:	5f 2e       	mov	r5, r31
     768:	28 0e       	add	r2, r24
     76a:	39 1e       	adc	r3, r25
     76c:	4a 1e       	adc	r4, r26
     76e:	5b 1e       	adc	r5, r27
      if (RXCalc < CC1000ControlM_FREQ_MIN || RXCalc > CC1000ControlM_FREQ_MAX) {
     770:	80 50       	subi	r24, 0x00	; 0
     772:	90 42       	sbci	r25, 0x20	; 32
     774:	a0 44       	sbci	r26, 0x40	; 64
     776:	b0 40       	sbci	r27, 0x00	; 0
     778:	80 50       	subi	r24, 0x00	; 0
     77a:	9c 49       	sbci	r25, 0x9C	; 156
     77c:	af 4b       	sbci	r26, 0xBF	; 191
     77e:	b0 40       	sbci	r27, 0x00	; 0
     780:	08 f0       	brcs	.+2      	; 0x784
     782:	64 c0       	rjmp	.+200    	; 0x84c
        continue;
        }
      TXCalc = RXCalc - CC1000ControlM_CorTbl[i];
     784:	a9 8d       	ldd	r26, Y+25	; 0x19
     786:	ba 8d       	ldd	r27, Y+26	; 0x1a
     788:	8d 91       	ld	r24, X+
     78a:	9c 91       	ld	r25, X
     78c:	aa 27       	eor	r26, r26
     78e:	bb 27       	eor	r27, r27
     790:	42 01       	movw	r8, r4
     792:	31 01       	movw	r6, r2
     794:	68 1a       	sub	r6, r24
     796:	79 0a       	sbc	r7, r25
     798:	8a 0a       	sbc	r8, r26
     79a:	9b 0a       	sbc	r9, r27
      if (TXCalc < CC1000ControlM_FREQ_MIN || TXCalc > CC1000ControlM_FREQ_MAX) {
     79c:	d4 01       	movw	r26, r8
     79e:	c3 01       	movw	r24, r6
     7a0:	80 50       	subi	r24, 0x00	; 0
     7a2:	90 40       	sbci	r25, 0x00	; 0
     7a4:	a0 44       	sbci	r26, 0x40	; 64
     7a6:	b0 40       	sbci	r27, 0x00	; 0
     7a8:	80 50       	subi	r24, 0x00	; 0
     7aa:	9c 49       	sbci	r25, 0x9C	; 156
     7ac:	af 4b       	sbci	r26, 0xBF	; 191
     7ae:	b0 40       	sbci	r27, 0x00	; 0
     7b0:	08 f0       	brcs	.+2      	; 0x7b4
     7b2:	4c c0       	rjmp	.+152    	; 0x84c
        continue;
        }
      Channel += NRef * FRef;
     7b4:	ca 01       	movw	r24, r20
     7b6:	b9 01       	movw	r22, r18
     7b8:	a6 01       	movw	r20, r12
     7ba:	95 01       	movw	r18, r10
     7bc:	0e 94 37 0f 	call	0x1e6e
     7c0:	dc 01       	movw	r26, r24
     7c2:	cb 01       	movw	r24, r22
     7c4:	e8 0e       	add	r14, r24
     7c6:	f9 1e       	adc	r15, r25
     7c8:	0a 1f       	adc	r16, r26
     7ca:	1b 1f       	adc	r17, r27
      Channel -= CC1000ControlM_IF;
     7cc:	20 e1       	ldi	r18, 0x10	; 16
     7ce:	36 eb       	ldi	r19, 0xB6	; 182
     7d0:	4d ef       	ldi	r20, 0xFD	; 253
     7d2:	5f ef       	ldi	r21, 0xFF	; 255
     7d4:	e2 0e       	add	r14, r18
     7d6:	f3 1e       	adc	r15, r19
     7d8:	04 1f       	adc	r16, r20

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