📄 syn_eras_str.tdf
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-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Workfile: syn_eras_str.tdf $
-- $Archive: P:/RS/units/Dec_str/ahdl/syn_eras_str.tdv $
--
-- $Revision: 1.3 $
-- $Date: 29 Oct 1999 18:45:20 $
-- $Author : Alejandro Diaz-Manero
--
-- Project : RS_eras
--
-- Description : Syndrome computation and erasures indication for streaming RS
-- decoder supporting erasures.
--
-- Copyright 1999 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
FUNCTION lpm_ram_dq (data[LPM_WIDTH-1..0], address[LPM_WIDTHAD-1..0], we,
inclock, outclock)
RETURNS (q[LPM_WIDTH-1..0]);
FUNCTION lpm_counter (data[LPM_WIDTH-1..0], clock, clk_en, cnt_en, updown, aclr,
aset, aconst, aload, sclr, sset, sconst, sload)
RETURNS (q[LPM_WIDTH-1..0], eq[15..0]);
FUNCTION gfmul (a[m..1], b[m..1])
RETURNS (c[m..1]);
PARAMETERS
(
n = 15, -- length of code ((check+1) to 255)
m = 4, -- GF size (2^m) (3 to 8)
irrpol = 19, -- field polynomial
check = 4, -- number of check symbols (= # of syndromes)
first_root, one_half,
root1 = 1, root2 = 2, root3 = 4, root4 = 8, root5 = 1, root6 = 3, root7 = 6, root8 = 12,
root9 = 15, root10 = 9, root11 = 13, root12 = 2, root13 = 10, root14 = 2, root15 = 11,
root16 = 3, root17 = 3, root18 = 6, root19 = 4, root20 = 8, root21 = 5, root22 = 12,
root23 = 0, root24 = 9, root25 = 8, root26 = 7, root27 = 5, root28 = 4, root29 = 9,
root30 = 8, root31 = 6, root32 = 7, root33 = 5, root34 = 3, root35 = 9, root36 = 8,
root37 = 1, root38 = 2, root39 = 9, root40 = 8, root41 = 6, root42 = 7, root43 = 5,
root44 = 3, root45 = 9, root46 = 5, root47 = 11, root48 = 12, root49 = 13, root50 = 3
);
constant size = ceil(log2(n+1));
constant wide = ceil(log2(check+1));
subdesign syn_eras_str
(
sysclk, reset, r[m..1], dsin, dsout, eras_ind : INPUT;
gofinal, massdone : INPUT;
errvec[check..1][m..1], errloc[check..1][size..1] : INPUT;
bypass : INPUT;
latchstage : OUTPUT;
resetmass, resetchn : OUTPUT;
rdyin, outvalid : OUTPUT;
eras_roots[check..1][m..1], num_eras[wide..1] : OUTPUT;
syn[check..1][m..1], rsout[m..1], badsym : OUTPUT;
)
VARIABLE
sh_alpha[check..1][m..1] : dffe;
multroot[m..1] : node;
rootpos[m..1] : dffe;
first_rootpos[m..1], one_div_bytwo[m..1] : node;
rr[m..1], reg[check..1][m..1], deldone, deladd[2..1][size..1] : dffe;
ovdel[4..1], rsoutff[m..1], readdone[3..1], bs : dff;
synout[check..1][m..1], mulout[check..1][m..1] : node;
alpha[check..1][m..1] : node;
addwrite[size..1], addread[size..1], wrzero[size..1], rdzero[size..1] : node;
dummy[m..1] : node;
dataone[m..1], datatwo[m..1], datathr[m..1], datafor[m..1] : node;
onemux[size..1], twomux[size..1], thrmux[size..1], formux[size..1] : node;
addeq[check..1][size..1], errmux[check..1][m..1] : node;
oval : node;
nval[size..1], zero[wide..1] : node;
bsnode[check..1], bserr[m..1] : node;
lcnta, lcntb : lpm_counter WITH (LPM_WIDTH = size, LPM_DIRECTION = "DOWN" );
cnt_eras : lpm_counter WITH (LPM_WIDTH = wide, LPM_DIRECTION = "UP" );
onein, twoin, thrin, forin : node;
oneout, twoout, throut, forout : node;
nextstage, clrstage, nextstate : node;
-- redundant clear bits for fan-out control
ss : MACHINE OF BITS (state[12..1])
WITH STATES (s0 = B"111000000000", -- clear all
s1 = B"000000000001", -- load one
s2 = B"000100000000", -- forward data
s3 = B"111000000000", -- clear
s4 = B"000000000010", -- load two
s5 = B"000100000000", -- forward data
s6 = B"111000000000", -- clear
s7 = B"000000000100", -- load three
s8 = B"000100000000", -- forward data
s9 = B"111000000000", -- clear
s10 = B"000000011000", -- load four and write one
s11 = B"000100000000", -- forward data
s12 = B"111000000000", -- clear
s13 = B"000000100001", -- load one and write two
s14 = B"000100000000", -- forward data
s15 = B"111000000000", -- clear
s16 = B"000001000010", -- load two and write three
s17 = B"000100000000", -- forward data
s18 = B"111000000000", -- clear
s19 = B"000010000100", -- load three and write four
s20 = B"000100000000", -- forward data
s21 = B"111000000000"); -- clear
BEGIN
nval[] = n;
ss.clk = sysclk;
ss.reset = reset;
-- writedone is !wrzero[size] delayed by 3 cycles
nextstate = gofinal & massdone & !wrzero[size] & readdone[3];
CASE ss IS
-- clear all
WHEN s0 => ss = s1;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s1;
-- END IF;
-- load ram 1
WHEN s1 =>
-- IF (reset == VCC) THEN
-- ss = s0;
IF (nextstate == VCC) THEN
ss = s2;
ELSE
ss = s1;
END IF;
WHEN s2 => ss = s3;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s3;
-- END IF;
WHEN s3 => ss = s4;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s4;
-- END IF;
-- load ram 2
WHEN s4 =>
-- IF (reset == VCC) THEN
-- ss = s0;
IF (nextstate == VCC) THEN
ss = s5;
ELSE
ss = s4;
END IF;
WHEN s5 => ss = s6;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s6;
-- END IF;
WHEN s6 => ss = s7;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s7;
-- END IF;
-- load ram 3
WHEN s7 =>
-- IF (reset == VCC) THEN
-- ss = s0;
IF (nextstate == VCC) THEN
ss = s8;
ELSE
ss = s7;
END IF;
WHEN s8 => ss = s9;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s9;
-- END IF;
WHEN s9 => ss = s10;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s10;
-- END IF;
-- *** loop starts here ***
-- load ram 4, write ram 1
WHEN s10 =>
-- IF (reset == VCC) THEN
-- ss = s0;
IF (nextstate == VCC) THEN
ss = s11;
ELSE
ss = s10;
END IF;
WHEN s11 => ss = s12;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s12;
-- END IF;
WHEN s12 => ss = s13;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s13;
-- END IF;
-- load ram 1, write ram 2
WHEN s13 =>
-- IF (reset == VCC) THEN
-- ss = s0;
IF (nextstate == VCC) THEN
ss = s14;
ELSE
ss = s13;
END IF;
WHEN s14 => ss = s15;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s15;
-- END IF;
WHEN s15 => ss = s16;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s16;
-- END IF;
-- load ram 2, write ram 3
WHEN s16 =>
-- IF (reset == VCC) THEN
-- ss = s0;
IF (nextstate == VCC) THEN
ss = s17;
ELSE
ss = s16;
END IF;
WHEN s17 => ss = s18;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s18;
-- END IF;
WHEN s18 => ss = s19;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s19;
-- END IF;
-- load ram 3, write ram 4
WHEN s19 =>
-- IF (reset == VCC) THEN
-- ss = s0;
IF (nextstate == VCC) THEN
ss = s20;
ELSE
ss = s19;
END IF;
WHEN s20 => ss = s21;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s21;
-- END IF;
WHEN s21 => ss = s10;
-- IF (reset == VCC) THEN
-- ss = s0;
-- ELSE
-- ss = s10;
-- END IF;
WHEN others =>
ss = s0;
END CASE;
onein = state[1];
twoin = state[2];
thrin = state[3];
forin = state[4];
oneout = state[5];
twoout = state[6];
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