📄 syn_std_str.tdf
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-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Workfile: syn_std_str.tdf $
-- $Archive: P:/RS_std/units/Dec_str/ahdl/syn_std_str.tdv $
--
-- $Revision: 1.0 $
-- $Date: 23 Jul 1999 15:14:32 $
-- $Author : Alejandro Diaz-Manero
--
-- Project : RS_std
--
-- Description :
--
-- Copyright 1999 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
FUNCTION lpm_ram_dq (data[LPM_WIDTH-1..0], address[LPM_WIDTHAD-1..0], we,
inclock, outclock)
RETURNS (q[LPM_WIDTH-1..0]);
FUNCTION lpm_counter (data[LPM_WIDTH-1..0], clock, clk_en, cnt_en, updown, aclr,
aset, aconst, aload, sclr, sset, sconst, sload)
RETURNS (q[LPM_WIDTH-1..0], eq[15..0]);
FUNCTION gfmul (a[m..1], b[m..1])
RETURNS (c[m..1]);
PARAMETERS
(
n = 204, -- length of code ((check+1) to 255)
m = 8, -- GF size (2^m) (3 to 8)
irrpol = 285, -- field polynomial
check = 16, -- number of check symbols (= # of syndromes) - (3 to 20)
root1 = 1, root2 = 2, root3 = 4, root4 = 8, root5 = 16, root6 = 32, root7 = 64, root8 = 128,
root9 = 29, root10 = 58, root11 = 116, root12 = 232, root13 = 205, root14 = 135, root15 = 19,
root16 = 38, root17 = 76, root18 = 152, root19 = 45, root20 = 90, root21 = 180, root22 = 117,
root23 = 234, root24 = 201, root25 = 143, root26 = 3, root27 = 6, root28 = 12, root29 = 24,
root30 = 48, root31 = 96, root32 = 192, root33 = 157, root34 = 39, root35 = 78, root36 = 156,
root37 = 37, root38 = 74, root39 = 148, root40 = 53, root41 = 106, root42 = 212, root43 = 181,
root44 = 119, root45 = 238, root46 = 193, root47 = 159, root48 = 35, root49 = 70, root50 = 140
);
constant errs = floor(check DIV 2);
constant size = ceil(log2(n+1));
subdesign syn_std_str
(
sysclk, reset, r[m..1], dsin, dsout : INPUT;
gofinal, massdone : INPUT;
errvec[errs..1][m..1], errloc[errs..1][size..1] : INPUT;
bypass : INPUT;
latchstage : OUTPUT;
resetmass, resetchn : OUTPUT;
rdyin, outvalid : OUTPUT;
syn[check..1][m..1], rsout[m..1], badsym : OUTPUT;
)
VARIABLE
rr[m..1], reg[check..1][m..1], deldone, deladd[2..1][size..1] : dffe;
ovdel[4..1], rsoutff[m..1], readdone[3..1], bs : dff;
synout[check..1][m..1], mulout[check..1][m..1] : node;
alpha[check..1][m..1] : node;
addwrite[size..1], addread[size..1], wrzero[size..1], rdzero[size..1] : node;
dummy[m..1] : node;
dataone[m..1], datatwo[m..1], datathr[m..1], datafor[m..1] : node;
onemux[size..1], twomux[size..1], thrmux[size..1], formux[size..1] : node;
addeq[errs..1][size..1], errmux[errs..1][m..1] : node;
oval : node;
nval[size..1] : node;
bsnode[errs..1], bserr[m..1] : node;
lcnta, lcntb : lpm_counter WITH (LPM_WIDTH = size, LPM_DIRECTION = "DOWN" );
onein, twoin, thrin, forin : node;
oneout, twoout, throut, forout : node;
nextstage, clrstage, nextstate : node;
-- redundant clear bits for fan-out control
ss : MACHINE OF BITS (state[12..1])
WITH STATES (s0 = B"111000000000", -- clear all
s1 = B"000000000001", -- load one
s2 = B"000100000000", -- forward data
s3 = B"111000000000", -- clear
s4 = B"000000000010", -- load two
s5 = B"000100000000", -- forward data
s6 = B"111000000000", -- clear
s7 = B"000000000100", -- load three
s8 = B"000100000000", -- forward data
s9 = B"111000000000", -- clear
s10 = B"000000011000", -- load four and write one
s11 = B"000100000000", -- forward data
s12 = B"111000000000", -- clear
s13 = B"000000100001", -- load one and write two
s14 = B"000100000000", -- forward data
s15 = B"111000000000", -- clear
s16 = B"000001000010", -- load two and write three
s17 = B"000100000000", -- forward data
s18 = B"111000000000", -- clear
s19 = B"000010000100", -- load three and write four
s20 = B"000100000000", -- forward data
s21 = B"111000000000"); -- clear
BEGIN
nval[] = n;
ss.clk = sysclk;
ss.reset = GND;
-- writedone is !wrzero[size] delayed by 3 cycles
nextstate = gofinal & massdone & !wrzero[size] & readdone[3];
CASE ss IS
-- clear all
WHEN s0 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s1;
END IF;
-- load ram 1
WHEN s1 =>
IF (reset == VCC) THEN
ss = s0;
ELSIF (nextstate == VCC) THEN
ss = s2;
ELSE
ss = s1;
END IF;
WHEN s2 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s3;
END IF;
WHEN s3 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s4;
END IF;
-- load ram 2
WHEN s4 =>
IF (reset == VCC) THEN
ss = s0;
ELSIF (nextstate == VCC) THEN
ss = s5;
ELSE
ss = s4;
END IF;
WHEN s5 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s6;
END IF;
WHEN s6 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s7;
END IF;
-- load ram 3
WHEN s7 =>
IF (reset == VCC) THEN
ss = s0;
ELSIF (nextstate == VCC) THEN
ss = s8;
ELSE
ss = s7;
END IF;
WHEN s8 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s9;
END IF;
WHEN s9 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s10;
END IF;
-- *** loop starts here ***
-- load ram 4, write ram 1
WHEN s10 =>
IF (reset == VCC) THEN
ss = s0;
ELSIF (nextstate == VCC) THEN
ss = s11;
ELSE
ss = s10;
END IF;
WHEN s11 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s12;
END IF;
WHEN s12 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s13;
END IF;
-- load ram 1, write ram 2
WHEN s13 =>
IF (reset == VCC) THEN
ss = s0;
ELSIF (nextstate == VCC) THEN
ss = s14;
ELSE
ss = s13;
END IF;
WHEN s14 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s15;
END IF;
WHEN s15 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s16;
END IF;
-- load ram 2, write ram 3
WHEN s16 =>
IF (reset == VCC) THEN
ss = s0;
ELSIF (nextstate == VCC) THEN
ss = s17;
ELSE
ss = s16;
END IF;
WHEN s17 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s18;
END IF;
WHEN s18 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s19;
END IF;
-- load ram 3, write ram 4
WHEN s19 =>
IF (reset == VCC) THEN
ss = s0;
ELSIF (nextstate == VCC) THEN
ss = s20;
ELSE
ss = s19;
END IF;
WHEN s20 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s21;
END IF;
WHEN s21 =>
IF (reset == VCC) THEN
ss = s0;
ELSE
ss = s10;
END IF;
WHEN others =>
ss = s0;
END CASE;
onein = state[1];
twoin = state[2];
thrin = state[3];
forin = state[4];
oneout = state[5];
twoout = state[6];
throut = state[7];
forout = state[8];
nextstage = state[9];
clrstage = state[10];
resetmass = state[11];
resetchn = state[12];
latchstage = nextstage;
rr[].clk = sysclk;
rr[] = r[] & !clrstage;
rr[].ena = (wrzero[size] & dsin) # clrstage;
reg[][].clk = sysclk;
reg[][].ena = (wrzero[size] & dsin) # clrstage;
FOR k IN 1 TO check GENERATE
synout[k][m..1] = rr[m..1] $ mulout[k][m..1];
END GENERATE;
reg[][] = synout[][] & !clrstage;
alpha[1][] = root1;
alpha[2][] = root2;
alpha[3][] = root3;
IF (check >= 4) GENERATE
alpha[4][] = root4;
END GENERATE;
IF (check >= 5) GENERATE
alpha[5][] = root5;
END GENERATE;
IF (check >= 6) GENERATE
alpha[6][] = root6;
END GENERATE;
IF (check >= 7) GENERATE
alpha[7][] = root7;
END GENERATE;
IF (check >= 8) GENERATE
alpha[8][] = root8;
END GENERATE;
IF (check >= 9) GENERATE
alpha[9][] = root9;
END GENERATE;
IF (check >= 10) GENERATE
alpha[10][] = root10;
END GENERATE;
IF (check >= 11) GENERATE
alpha[11][] = root11;
END GENERATE;
IF (check >= 12) GENERATE
alpha[12][] = root12;
END GENERATE;
IF (check >= 13) GENERATE
alpha[13][] = root13;
END GENERATE;
IF (check >= 14) GENERATE
alpha[14][] = root14;
END GENERATE;
IF (check >= 15) GENERATE
alpha[15][] = root15;
END GENERATE;
IF (check >= 16) GENERATE
alpha[16][] = root16;
END GENERATE;
IF (check >= 17) GENERATE
alpha[17][] = root17;
END GENERATE;
IF (check >= 18) GENERATE
alpha[18][] = root18;
END GENERATE;
IF (check >= 19) GENERATE
alpha[19][] = root19;
END GENERATE;
IF (check >= 20) GENERATE
alpha[20][] = root20;
END GENERATE;
IF (check >= 21) GENERATE
alpha[21][] = root21;
END GENERATE;
IF (check >= 22) GENERATE
alpha[22][] = root22;
END GENERATE;
IF (check >= 23) GENERATE
alpha[23][] = root23;
END GENERATE;
IF (check >= 24) GENERATE
alpha[24][] = root24;
END GENERATE;
IF (check >= 25) GENERATE
alpha[25][] = root25;
END GENERATE;
IF (check >= 26) GENERATE
alpha[26][] = root26;
END GENERATE;
IF (check >= 27) GENERATE
alpha[27][] = root27;
END GENERATE;
IF (check >= 28) GENERATE
alpha[28][] = root28;
END GENERATE;
IF (check >= 29) GENERATE
alpha[29][] = root29;
END GENERATE;
IF (check >= 30) GENERATE
alpha[30][] = root30;
END GENERATE;
IF (check >= 31) GENERATE
alpha[31][] = root31;
END GENERATE;
IF (check >= 32) GENERATE
alpha[32][] = root32;
END GENERATE;
IF (check >= 33) GENERATE
alpha[33][] = root33;
END GENERATE;
IF (check >= 34) GENERATE
alpha[34][] = root34;
END GENERATE;
IF (check >= 35) GENERATE
alpha[35][] = root35;
END GENERATE;
IF (check >= 36) GENERATE
alpha[36][] = root36;
END GENERATE;
IF (check >= 37) GENERATE
alpha[37][] = root37;
END GENERATE;
IF (check >= 38) GENERATE
alpha[38][] = root38;
END GENERATE;
IF (check >= 39) GENERATE
alpha[39][] = root39;
END GENERATE;
IF (check >= 40) GENERATE
alpha[40][] = root40;
END GENERATE;
IF (check >= 41) GENERATE
alpha[41][] = root41;
END GENERATE;
IF (check >= 42) GENERATE
alpha[42][] = root42;
END GENERATE;
IF (check >= 43) GENERATE
alpha[43][] = root43;
END GENERATE;
IF (check >= 44) GENERATE
alpha[44][] = root44;
END GENERATE;
IF (check >= 45) GENERATE
alpha[45][] = root45;
END GENERATE;
IF (check >= 46) GENERATE
alpha[46][] = root46;
END GENERATE;
IF (check >= 47) GENERATE
alpha[47][] = root47;
END GENERATE;
IF (check >= 48) GENERATE
alpha[48][] = root48;
END GENERATE;
IF (check >= 49) GENERATE
alpha[49][] = root49;
END GENERATE;
IF (check >= 50) GENERATE
alpha[50][] = root50;
END GENERATE;
FOR k IN 1 TO check GENERATE
mulout[k][] = gfmul(reg[k][],alpha[k][]) WITH (irrpol=irrpol,m=m);
END GENERATE;
syn[][] = synout[][];
addwrite[] = lcnta.q[];
lcnta.data[] = nval[];
lcnta.clock = sysclk;
lcnta.cnt_en = (wrzero[size] & dsin);
lcnta.sload = clrstage;
addread[] = lcntb.q[];
lcntb.data[] = nval[];
lcntb.clock = sysclk;
lcntb.cnt_en = (rdzero[size] & dsout);
lcntb.sload = clrstage;
wrzero[1] = addwrite[1];
FOR k IN 2 TO size GENERATE
wrzero[k] = wrzero[k-1] # addwrite[k];
END GENERATE;
rdzero[1] = addread[1];
FOR k IN 2 TO size GENERATE
rdzero[k] = rdzero[k-1] # addread[k];
END GENERATE;
readdone[].clk = sysclk;
readdone[1] = !rdzero[size] & !clrstage;
readdone[2] = readdone[1] & !clrstage;
readdone[3] = readdone[2] & !clrstage;
--readdone[].clrn = !clrstage;
deldone.clk = sysclk;
deldone = wrzero[size] & !clrstage; -- write last symbol
--deldone.clrn = !clrstage;
dataone[] = lpm_ram_dq ( rr[], onemux[], (deldone & onein),sysclk,sysclk)
WITH (LPM_WIDTH = m, LPM_WIDTHAD = size, LPM_INDATA = "REGISTERED",
LPM_ADDRESS_CONTROL = "REGISTERED", LPM_OUTDATA = "REGISTERED");
datatwo[] = lpm_ram_dq ( rr[], twomux[], (deldone & twoin),sysclk,sysclk)
WITH (LPM_WIDTH = m, LPM_WIDTHAD = size, LPM_INDATA = "REGISTERED",
LPM_ADDRESS_CONTROL = "REGISTERED", LPM_OUTDATA = "REGISTERED");
datathr[] = lpm_ram_dq ( rr[], thrmux[], (deldone & thrin),sysclk,sysclk)
WITH (LPM_WIDTH = m, LPM_WIDTHAD = size, LPM_INDATA = "REGISTERED",
LPM_ADDRESS_CONTROL = "REGISTERED", LPM_OUTDATA = "REGISTERED");
datafor[] = lpm_ram_dq ( rr[], formux[], (deldone & forin),sysclk,sysclk)
WITH (LPM_WIDTH = m, LPM_WIDTHAD = size, LPM_INDATA = "REGISTERED",
LPM_ADDRESS_CONTROL = "REGISTERED", LPM_OUTDATA = "REGISTERED");
onemux[] = (addwrite[] & onein) # (addread[] & oneout);
twomux[] = (addwrite[] & twoin) # (addread[] & twoout);
thrmux[] = (addwrite[] & thrin) # (addread[] & throut);
formux[] = (addwrite[] & forin) # (addread[] & forout);
-- delay address 2clks to line up add with data output
deladd[][].clk = sysclk;
deladd[1][] = addread[] & !clrstage;
deladd[2][] = deladd[1][] & !clrstage;
--deladd[][].clrn = !clrstage;
FOR j IN 1 TO errs GENERATE
addeq[j][1] = errloc[j][1] $ deladd[2][1];
FOR k IN 2 TO size GENERATE
addeq[j][k] = addeq[j][k-1] # (errloc[j][k] $ deladd[2][k]);
END GENERATE;
END GENERATE;
errmux[1][] = errvec[1][] & !(addeq[1][size]);
FOR k IN 2 TO errs GENERATE
errmux[k][] = errmux[k-1][] # (errvec[k][] & !(addeq[k][size]));
END GENERATE;
dummy[] = (dataone[] & oneout) #
(datatwo[] & twoout) #
(datathr[] & throut) #
(datafor[] & forout);
rsoutff[].clk = sysclk;
FOR k IN 1 TO m GENERATE
rsoutff[k] = (dummy[k] $ (errmux[errs][k] & !bypass)) & !clrstage;
END GENERATE;
--rsoutff[].clrn = !clrstage;
rsout[] = rsoutff[];
bsnode[1] = !addeq[1][size];
FOR k IN 2 TO errs GENERATE
bsnode[k] = !addeq[k][size] # bsnode[k-1];
END GENERATE;
bserr[1] = errmux[errs][1];
FOR k IN 2 TO m GENERATE
bserr[k] = errmux[errs][k] # bserr[k-1];
END GENERATE;
-- don't indicate error if errval = 0
bs = bsnode[errs] & bserr[m];
bs.clk = sysclk;
badsym = bs;
-- unless output state, outvalid stays low
oval = rdzero[size] & (state[5] # state[6] # state[7] # state[8]);
ovdel[].clk = sysclk;
ovdel[1] = oval & !clrstage;
ovdel[2] = ovdel[1] & !clrstage;
ovdel[3] = ovdel[2] & !clrstage;
ovdel[4] = ovdel[3] & !clrstage;
--ovdel[].clrn = !clrstage;
outvalid = ovdel[4];
rdyin = wrzero[size];
END;
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