mmx_chp2.htm

MMX即多媒体可扩展指令集

<TD bgcolor="#000000" WIDTH=96><CENTER><B><small>Decimal</small></B></CENTER></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=175><small>Byte</small></TD><TD bgcolor="#000000" WIDTH=88><small>80H</small></TD>
<TD bgcolor="#000000" WIDTH=76><small>-128</small></TD><TD bgcolor="#000000" WIDTH=90><small>7FH</small></TD>
<TD bgcolor="#000000" WIDTH=96><small>127</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=175><small>Word</small></TD><TD bgcolor="#000000" WIDTH=88><small>8000H</small></TD>
<TD bgcolor="#000000" WIDTH=76><small>-32,768</small></TD><TD bgcolor="#000000" WIDTH=90><small>7FFFH</small></TD>
<TD bgcolor="#000000" WIDTH=96><small>32,767</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=175><CENTER><B><small>Unsigned</small></B></CENTER></TD>
<TD bgcolor="#000000" WIDTH=88></TD><TD bgcolor="#000000" WIDTH=76></TD><TD bgcolor="#000000" WIDTH=90></TD><TD bgcolor="#000000" WIDTH=96></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=175><small>Byte</small></TD><TD bgcolor="#000000" WIDTH=88><small>00H</small></TD>
<TD bgcolor="#000000" WIDTH=76><small>0</small></TD><TD bgcolor="#000000" WIDTH=90><small>FFH</small></TD>
<TD bgcolor="#000000" WIDTH=96><small>255</small></TD></TR>

<TR><TD bgcolor="#000000" WIDTH=175><small>Word</small></TD><TD bgcolor="#000000" WIDTH=88><small>0000H</small></TD>
<TD bgcolor="#000000" WIDTH=76><small>0</small></TD><TD bgcolor="#000000" WIDTH=90><small>FFFFH</small></TD>
<TD bgcolor="#000000" WIDTH=96><small>65,535</small></TD></TR>
</table>
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<br>
MMX instructions do not indicate overflow or underflow occurrence by generating exceptions or setting flags.

<H3><a name="2.4.3">2.4.3 INSTRUCTION GROUP OVERVIEW</a></H3>

This section provides an overview of the MMX instruction groups. See Chapter 5 for detailed information on the instructions, including information on encoding, operation, and exceptions. The fifty-seven new MMX instructions are grouped into these categories:

<ul>
<li>Arithmetic Instructions
<li>Comparison Instructions
<li>Conversion Instructions
<li>Logical Instructions
<li>Shift Instructions
<li>Data Transfer Instructions
<li>Empty MMX State (EMMS) Instruction
</ul>

<H4><a name="2.4.3.1">2.4.3.1 Arithmetic Instructions</a></H4>

<B>Packed Addition and Subtraction</B><br><br>

The PADD (Packed Add) and PSUB (Packed Subtract) instructions add or subtract the signed or unsigned data elements of the source operand to or from the destination operand in wrap- around mode. These instructions support packed byte, packed word, and packed doubleword data types.<br><br>

The PADDS (Packed Add with Saturation) and PSUBS (Packed Subtract with Saturation) instructions add or subtract the signed data elements of the source operand to or from the signed data elements of the destination operand and saturate the result to the limits of the signed data-type range. These instructions support packed byte and packed word data types.<br><br>

The PADDUS (Packed Add Unsigned with Saturation) and PSUBUS (Packed Subtract Unsigned with Saturation) instructions add or subtract the unsigned data elements of the source operand to or from the unsigned data elements of the destination operand and saturate the result to the limits of the unsigned data-type range. These instructions support packed byte and packed word data types.<br><br>

<B>Packed Multiplication</B><br><br>

Packed multiplication instructions perform four multiplications on pairs of signed 16-bit operands, producing 32-bit intermediate results. Users may choose the low-order or high-order parts of each 32-bit result.<br><br>

The PMULHW (Packed Multiply High) and PMULLW (Packed Multiply Low) instructions multiply the signed words of the source and destination operands and write the high-order or low-order 16 bits of each of the results to the destination operand.<br><br>

<B>Packed Multiply Add</B><br><br>

The PMADDWD (Packed Multiply and Add) instruction calculates the products of the signed words of the source and destination operands. The four intermediate 32-bit doubleword products are summed in pairs to produce two 32-bit doubleword results.
 
<H4><a name="2.4.3.2">2.4.3.2 Comparison Instructions</a></H4>

The PCMPEQ (Packed Compare for Equal) and PCMPGT (Packed Compare for Greater Than) instructions compare the corresponding data elements in the source and destination operands for equality or value greater than, respectively. These instructions generate a mask of ones or zeros which are written to the destination operand. Logical operations can use the mask to select elements. This can be used to implement a packed conditional move operation without a branch or a set of branch instructions. No flags are set.<br><br>

These instructions support packed byte, packed word and packed doubleword data types.

<H4><a name="2.4.3.3">2.4.3.3 Conversion Instructions</a></H4>

<B>Pack and Unpack</B><br><br>

The Pack and Unpack instructions perform conversions between the packed data types.<br><br>

The PACKSS (Packed with Signed Saturation) instruction converts signed words into signed bytes or signed doublewords into signed words, in signed saturation mode.<br><br>

The PACKUS (Packed with Unsigned Saturation) instruction converts signed words into unsigned bytes, in unsigned saturation mode.<br><br>

The PUNPCKH (Unpack High Packed Data) and PUNPCKL (Unpack Low Packed Data) instructions convert bytes to words, words to doublewords, or doublewords to quadwords.

<H4><a name="2.4.3.4">2.4.3.4 Logical Instructions</a></H4>

The PAND (Bitwise Logical And), PANDN (Bitwise Logical And Not), POR (Bitwise Logical OR), and PXOR (Bitwise Logical Exclusive OR) instructions perform bitwise logical operations on 64-bit quantities.

<H4><a name="2.4.3.5">2.4.3.5 Shift Instructions</a></H4>

The logical shift left, logical shift right and arithmetic shift right instructions shift each element by a specified number of bits. The logical left and right shifts also enable a 64-bit quantity (quadword) to be shifted as one block, assisting in data type conversions and alignment operations.<br><br>

The PSLL (Packed Shift Left Logical) and PSRL (Packed Shift Right Logical) instructions perform a logical left or right shift, and fill the empty high or low order bit positions with zeros. These instructions support packed word, packed doubleword, and quadword data types.<br><br>

The PSRA (Packed Shift Right Arithmetic) instruction performs an arithmetic right shift, copying the sign bit into empty bit positions on the upper end of the operand. This instruction supports packed word and packed doubleword data types.<br><br>
 
<H4><a name="2.4.3.6">2.4.3.6 Data Transfer Instructions</a></H4>

The MOVD (Move 32 Bits) instruction transfers 32 bits of packed data from memory to MMX registers and visa versa, or from integer registers to MMX registers and visa versa.<br><br>

The MOVQ (Move 64 Bits) instruction transfers 64-bits of packed data from memory to MMX registers and vise versa, or transfers data between MMX registers.<br><br>

<H4><a name="2.4.3.7">2.4.3.7 EMMS (Empty MMX&#153; State) Instructions</a></H4>

The EMMS instruction empties the MMX state. This instruction must be used to clear the IA MMX state (empty the floating-point tag word) at the end of an MMX routine before calling other routines that can execute floating-point instructions.

<H3><a name="2.4.4">2.4.4 INSTRUCTION OPERAND</a></H3>

All MMX instructions, except the EMMS instruction, reference and operate on two operands: the source and destination operands.  The right operand is the source and the left operand is the destination.  The destination operand may also be a second source operand for the operation. The instruction overwrites the destination operand with the result.<br><br>

For example, a two-operand instruction would be decoded as:<br><br>

<center><small><b>DEST (left operand) OP SRC (right operand)</b></small></center><br>

The source operand for all the MMX instructions (except the data transfer instructions), can reside either in memory or in an MMX register. The destination operand resides in an MMX register.<br><br>

For data transfer instructions, the source and destination operands can also be an integer register (for the MOVD instruction) or memory location (for both the MOVD and MOVQ instructions).

<H3><a name="2.5">2.5 COMPATIBILITY</a></H3>

The IA MMX state is aliased upon the IA floating-point state. No new state or mode is added to support the MMX technology. The same floating-point instructions that save and restore the floating-point state also handle the IA MMX state (for example, during context switching).<br><br>

MMX technology uses the same interface techniques between the floating-point architecture and the operating system (primarily for task switching purposes). For more detail, see Section 4.1.

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