📄 uart_hw.h
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#define UART2_MSR (UART2_base+0x18)
#define UART2_SCR (UART2_base+0x1c)
#define UART2_DLL (UART2_base+0x0)
#define UART2_DLH (UART2_base+0x4)
#define UART2_EFR (UART2_base+0x8) /* Only when LCR = 0xbf */
#define UART2_XON1 (UART2_base+0x10) /* Only when LCR = 0xbf */
#define UART2_XON2 (UART2_base+0x14) /* Only when LCR = 0xbf */
#define UART2_XOFF1 (UART2_base+0x18) /* Only when LCR = 0xbf */
#define UART2_XOFF2 (UART2_base+0x1c) /* Only when LCR = 0xbf */
#ifdef MT6205B
#define UART2_RATE_STEP (UART2_base+0x20)
#define UART2_STEP_COUNT (UART2_base+0x24)
#define UART2_SAMPLE_COUNT (UART2_base+0x28)
#endif /*MT6205B*/
#if ( (defined(MT6218)) || (defined(MT6218B)) || (defined(MT6219))|| (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define UART2_AUTOBAUD_EN (UART2_base+0x20)
#define UART2_RATE_STEP (UART2_base+0x24)
#define UART2_STEP_COUNT (UART2_base+0x28)
#define UART2_SAMPLE_COUNT (UART2_base+0x2c)
#define UART2_AUTOBAUD_REG (UART2_base+0x30)
#define UART2_AUTO_BAUDSAMPLE(UART2_base) (UART2_base+0x38)
#endif /*MT6218*/
#if ( (defined(MT6218B)) || (defined(MT6219)) || (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define UART2_RXDMA(UART2_base) (UART2_base+0x4c)
#endif
#if ( (defined(MT6218)) || (defined(MT6218B)) || (defined(MT6219))|| (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define UART3_RBR (UART3_base+0x0) /* Read only */
#define UART3_THR (UART3_base+0x0) /* Write only */
#define UART3_IER (UART3_base+0x4)
#define UART3_IIR (UART3_base+0x8) /* Read only */
#define UART3_FCR (UART3_base+0x8) /* Write only */
#define UART3_LCR (UART3_base+0xc)
#define UART3_MCR (UART3_base+0x10)
#define UART3_LSR (UART3_base+0x14)
#define UART3_MSR (UART3_base+0x18)
#define UART3_SCR (UART3_base+0x1c)
#define UART3_DLL (UART3_base+0x0)
#define UART3_DLH (UART3_base+0x4)
#define UART3_EFR (UART3_base+0x8) /* Only when LCR = 0xbf */
#define UART3_XON1 (UART3_base+0x10) /* Only when LCR = 0xbf */
#define UART3_XON2 (UART3_base+0x14) /* Only when LCR = 0xbf */
#define UART3_XOFF1 (UART3_base+0x18) /* Only when LCR = 0xbf */
#define UART3_XOFF2 (UART3_base+0x1c) /* Only when LCR = 0xbf */
#define UART3_AUTOBAUD_EN (UART3_base+0x20)
#define UART3_RATE_STEP (UART3_base+0x24)
#define UART3_STEP_COUNT (UART3_base+0x28)
#define UART3_SAMPLE_COUNT (UART3_base+0x2c)
#define UART3_AUTOBAUD_REG (UART3_base+0x30)
#define UART3_AUTO_BAUDSAMPLE(UART3_base) (UART3_base+0x38)
#endif /*MT6218*/
#if ( (defined(MT6218B)) || (defined(MT6219)) || (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227)) ||defined(MT6226M)
#define UART3_RXDMA(UART3_base) (UART3_base+0x4c)
#endif /*MT6218*/
//IER
#define UART_IER_ERBFI 0x0001
#define UART_IER_ETBEI 0x0002
#define UART_IER_ELSI 0x0004
#define UART_IER_EDSSI 0x0008
#define UART_IER_XOFFI 0x0020
#define UART_IER_RTSI 0x0040
#define UART_IER_CTSI 0x0080
#ifdef MT6208
#define UART1_IER_HW_NORMALINTS 0x000d
#define UART1_IER_HW_ALLINTS 0x000f
#define UART1_IER_SW_NORMALINTS 0x002d
#define UART1_IER_SW_ALLINTS 0x002f
/*Disable MSR interrupt*/
#define UART2_IER_HW_NORMALINTS 0x0005
#define UART2_IER_HW_ALLINTS 0x0007
#define UART2_IER_SW_NORMALINTS 0x0025
#define UART2_IER_SW_ALLINTS 0x0027
#endif /*(MT6208)*/
#if ( (defined(MT6205)) || (defined(MT6205B)) || (defined(MT6218)) || (defined(MT6218B)) || (defined(FPGA))|| (defined(MT6219))|| (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define IER_HW_NORMALINTS 0x000d
#define IER_HW_ALLINTS 0x000f
#define IER_SW_NORMALINTS 0x002d
#define IER_SW_ALLINTS 0x002f
#endif /*(MT6205,MT6205B)*/
#define UART_IER_ALLOFF 0x0000
#define UART_IER_VFIFO 0x0001
#if ( (defined(MT6205B)) || (defined(MT6218)) || (defined(MT6218B))|| (defined(MT6219)) || (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define UART_RATE_STEP_16 0x0000 /* baud = clock/UART_RATE_STEP/divisor */
#define UART_RATE_STEP_8 0x0001
#define UART_RATE_STEP_4 0x0002
#define UART_RATE_STEP_COUNT 0x0003 /* baud = clock/UART_RATE_STEP_COUNT */
#define UART_STEP_COUNT_MASK 0x00ff
#define UART_SAMPLE_COUNT_MASK 0x00ff
#endif /*MT6205B,MT6218*/
//FCR
#define UART_FCR_FIFOEN 0x0001
#define UART_FCR_CLRR 0x0002
#define UART_FCR_CLRT 0x0004
#define UART_FCR_FIFOINI 0x0007
#define UART_FCR_RX1Byte_Level 0x0000
#define UART_FCR_RX16Byte_Level 0x0040
#define UART_FCR_RX32Byte_Level 0x0080
#define UART_FCR_RX62Byte_Level 0x00c0
#define UART_FCR_TX1Byte_Level 0x0000
#define UART_FCR_TX16Byte_Level 0x0010
#define UART_FCR_TX32Byte_Level 0x0020
#define UART_FCR_TX62Byte_Level 0x0030
#if ( (defined(SLEEP_DONT_CARE_DBG_INFO)) || (defined(__PRODUCTION_RELEASE__)) )
#if ( (defined(MT6205)) || (defined(FPGA)) )
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI)
#define UART1_TxFIFO_DEPTH 16
#define UART1_RxFIFO_DEPTH 16
#define UART2_TxFIFO_DEPTH 4
#define UART2_RxFIFO_DEPTH 16
#endif /*MT6205,FPGA*/
#if ( (defined(MT6218)) || (defined(MT6218B))|| (defined(MT6219)) || (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
#define UART1_TxFIFO_DEPTH 16
#define UART1_RxFIFO_DEPTH 24
#define UART2_TxFIFO_DEPTH 4
#define UART2_RxFIFO_DEPTH 24
#define UART_VFIFO_DEPTH 7
#endif /*MT6218*/
#ifdef MT6205B
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
#define UART1_TxFIFO_DEPTH 16
#define UART1_RxFIFO_DEPTH 24
#define UART2_TxFIFO_DEPTH 4
#define UART2_RxFIFO_DEPTH 24
#endif /*MT6205B*/
#ifdef MT6208
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI)
#define UART_TxFIFO_DEPTH 64
#define UART_RxFIFO_DEPTH 32
#endif /*(MT6208)*/
#else /*!SLEEP_DONT_CARE_DBG_INFO*/
#if ( (defined(MT6205)) || (defined(FPGA)) )
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI)
#define UART1_TxFIFO_DEPTH 16
#define UART1_RxFIFO_DEPTH 16
#define UART2_TxFIFO_DEPTH 4
#define UART2_RxFIFO_DEPTH 16
#endif /*MT6205,FPGA*/
#if ( (defined(MT6218)) || (defined(MT6218B)) || (defined(MT6219))|| (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
#define UART1_TxFIFO_DEPTH 16
#define UART1_RxFIFO_DEPTH 24
#define UART2_TxFIFO_DEPTH 4
#define UART2_RxFIFO_DEPTH 24
#define UART_VFIFO_DEPTH 7
#endif /*MT6218*/
#ifdef MT6205B
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
#define UART1_TxFIFO_DEPTH 16
#define UART1_RxFIFO_DEPTH 24
#define UART2_TxFIFO_DEPTH 4
#define UART2_RxFIFO_DEPTH 24
#endif /*MT6205B*/
#ifdef MT6208
#define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI)
#define UART_TxFIFO_DEPTH 64
#define UART_RxFIFO_DEPTH 32
#endif /*(MT6208)*/
#endif /*SLEEP_DONT_CARE_DBG_INFO*/
//IIR,RO
#define UART_IIR_INT_INVALID 0x0001
#define UART_IIR_RLS 0x0006 // Receiver Line Status
#define UART_IIR_RDA 0x0004 // Receive Data Available
#define UART_IIR_CTI 0x000C // Character Timeout Indicator
#define UART_IIR_THRE 0x0002 // Transmit Holding Register Empty
#define UART_IIR_MS 0x0000 // Check Modem Status Register
#define UART_IIR_SWFlowCtrl 0x0010 // Receive XOFF characters
#define UART_IIR_HWFlowCtrl 0x0020 // CTS or RTS Rising Edge
#define UART_IIR_FIFOS_ENABLED 0x00c0
#define UART_IIR_NO_INTERRUPT_PENDING 0x0001
#define UART_IIR_INT_MASK 0x001f
//===============================LCR================================
//WLS
#define UART_WLS_8 0x0003
#define UART_WLS_7 0x0002
#define UART_WLS_6 0x0001
#define UART_WLS_5 0x0000
#define UART_DATA_MASK 0x0003
//Parity
#define UART_NONE_PARITY 0x0000
#define UART_ODD_PARITY 0x0008
#define UART_EVEN_PARITY 0x0018
#define UART_MARK_PARITY 0x0028
#define UART_SPACE_PARITY 0x0038
#define UART_PARITY_MASK 0x0038
//Stop bits
#define UART_1_STOP 0x0000
#define UART_1_5_STOP 0x0004 // Only valid for 5 data bits
#define UART_2_STOP 0x0004
#define UART_STOP_MASK 0x0004
#define UART_LCR_DLAB 0x0080
#define UART_LCR_BREAK 0x0040
//===============================LCR================================
//MCR
#define UART_MCR_DTR 0x0001
#define UART_MCR_RTS 0x0002
#define UART_MCR_LOOPB 0x0010
#define UART_MCR_IRE 0x0040 //Enable IrDA modulation/demodulation
#define UART_MCR_XOFF 0x0080
#define UART_MCR_Normal (UART_MCR_DTR | UART_MCR_RTS)
//LSR
#define UART_LSR_DR 0x0001
#define UART_LSR_OE 0x0002
#define UART_LSR_PE 0x0004
#define UART_LSR_FE 0x0008
#define UART_LSR_BI 0x0010
#define UART_LSR_THRE 0x0020
#define UART_LSR_TEMT 0x0040
#define UART_LSR_FIFOERR 0x0080
//MSR
#define UART_MSR_DCTS 0x0001
#define UART_MSR_DDSR 0x0002
#define UART_MSR_TERI 0x0004
#define UART_MSR_DDCD 0x0008
#define UART_MSR_CTS 0x0010
#define UART_MSR_DSR 0x0020
#define UART_MSR_RI 0x0040
#define UART_MSR_DCD 0x0080
//DLL
//DLM
//EFR
#define UART_EFR_AutoCTS 0x0080
#define UART_EFR_AutoRTS 0x0040
#define UART_EFR_Enchance 0x0010
#define UART_EFR_SWCtrlMask 0x000f
#define UART_EFR_NoSWFlowCtrl 0x0000
#define UART_EFR_ALLOFF 0x0000
#define UART_EFR_AutoRTSCTS 0x00c0
//Tx/Rx XON1/Xoff1 as flow control word
#define UART_EFR_SWFlowCtrlX1 0x000a
//Tx/Rx XON2/Xoff2 as flow control word
#define UART_EFR_SWFlowCtrlX2 0x0005
//Tx/Rx XON1&XON2/Xoff1&Xoff2 as flow control word
#define UART_EFR_SWFlowCtrlXAll 0x000f
/*AutoBaud*/
#if ( (defined(MT6218)) || (defined(MT6218B)) || (defined(MT6219))|| (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define AUTOBAUD_EN 0x1
#define AUTOBAUDSAMPLE_13M 0x6
#define AUTOBAUDSAMPLE_26M 0xd
#define AUTOBAUDSAMPLE_52M 0x1b
#endif /*MT6218, MT6218B*/
#if ( (defined(MT6218B)) || (defined(MT6219)) || (defined(MT6217))|| (defined(MT6228))|| defined(MT6229) || defined(MT6230))|| (defined(MT6226))|| (defined(MT6227))||defined(MT6226M)
#define UART_RXDMA_ON 0x0001
#define UART_RXDMA_OFF 0x0000
#define UART_RXDMA_TIMEOUT 0x0002
#endif
#endif
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