📄 post.lst
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C51 COMPILER V6.23a POST 09/10/2004 16:09:01 PAGE 1
C51 COMPILER V6.23a, COMPILATION OF MODULE POST
OBJECT MODULE PLACED IN POST.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE POST.C OPTIMIZE(6,SIZE) ORDER DEFINE(DEBUGMSG=0,DEBUGTOOL=0) DEBUG OBJECTEX
-TEND CODE SYMBOLS
stmt level source
1 /************************************************
2 * *
3 * POST.C: Power-up reset routine *
4 * *
5 ************************************************/
6
7 #include <reg51.h>
8 #include "mascot.h"
9 #include "osd.h"
10 #include "global.h"
11
12
13
14 //
15 // Register table for POST init
16 //
17 unsigned char code postInitTable[] = {
18
19 6, 0x25,
20 #if NEW_ADC
21 0xFC,0x11,0x14, //CR25-27
22 0x00,0x10,0x1A, //CR28-2A
23 #else
0xFC,0x10,0x12, //CR25-27
0x00,0x10,0x1A, //CR28-2A
#endif
27
28 11, 0x12, //CR12: ADC
29 0x3A, 0x30, //R: OFFSET, COARSER, FINE
30 0x3A, 0x30, //G: OFFSET, COARSER, FINE
31 0x3A, 0x30, //B: OFFSET, COARSER, FINE
32 0x02, //CR18
33 0xF2, //CR19 VCO=10111010: Z=101(4K) Vco=11(100MHz/V)
34 0xA0, //CR1A DIVIDER: 1344
35 0x48, //CR1B: PhaseA
36 0x94, //HIDE THE RETRACE LINE
37
38 1, 0x08,
39 0x08,
40
41 5, 0x2B, //CR2B-2F: DCLK REGISTERS
42 0x0C, //CR2B: M Divier DCLK, 65M
43 0x41,0x00, //CR2C,CR2D Ndivider
44 0x32,0x80, //CR2E-2F
45
46
47 5, 0x20, // Minify
48 0x00, 0x00, 0x00, 0x00, //CR20-CR23
49 #if (USE_TCON + USE_RSDS)
0x00, //CR24
#else
52 0xC0, //CR24
53 #endif
54
C51 COMPILER V6.23a POST 09/10/2004 16:09:01 PAGE 2
55 16, 0x30, // Capture Interface
56 0x03, //CR30
57 0x00, //CR31
58 0x07, //CR32: -H/-V
59 0x00, //CR33
60 0xA5,0x00,0x1D,0x00, //CR34-37: Capture H/V Start
61 0xFF,0x03,0xFF,0x02, //CR38-3B: Capture Width/Height
62 0xFF, //CR3C: Capture FIFO Depth, width/4-1
63 0x01,0x00,0x05, //CR3D-3F: Clamp
64
65
66
67 #if PANEL_1280
16, 0x40, // Display Interface
0x60, //CR40
0xA8,0x9F,0xA2,0x26, //CR41-CR44: Hort
0x2A,0xFF,0x34,0x01,0x04,0x04, //CR45-4A: Vert
0x00,0x00,0x00,0x00, //CR4B-4E: H/V Zoom
0x76, //CR4F
#else
75 16, 0x40, //CR40-4E: Display Interface
76 0x00, //CR40
77 0xA8,0x7F,0x82,0x11, //CR41-CR44: Hort
78 0x26,0xFF,0x23,0x03,0x03,0x86, //CR45-4A: Vert
79 0x00,0x00,0x00,0x00, //CR4B-4E: H/V Zoom
80 0x76, //CR4F
81 #endif
82
83
84 9, 0x50, // Panel Interface
85 #if MVXPRL_HT17L
0x86+(USE_GAMMA*8), //CR50: TFT 18-bit double_pixel, dithering on
0x00, //CR51
#elif (MVXPRL_CPT15R+AOC_CPTXG08_RSDS)
0x47+(USE_GAMMA*8), //CR50: TFT 18-bit single_pixel, dithering on
0x04, //CR51
#elif (CPT_CLAA170EA03)
0x46+(USE_GAMMA*8), //CR50: TFT 18-bit double_pixel, dithering on
0x00, //CR51
#elif (MVRL_SANYO15 + MVRL_NEC15)
95 0x01+(USE_GAMMA*8), //CR50: TFT 18-bit single_pixel, dithering off
96 0x04, //CR51
97 #elif (MVPL_CMO17+MVRL_1920)
0x80+(USE_GAMMA*8), //CR50: TFT 24-bit double_pixel, dithering off
0x00,
#else
0x06+(USE_GAMMA*8), //CR50: TFT 18-bit double_pixel, dithering on
0x00, //CR51
#endif
104
105 0x00,0x00,0x00, //CR52-54: Contrast Adjustment
106 0x00,0x00,0x00, //CR55-57: Background Color
107 0x00, //CR58
108
109
110 3, 0x80, // USE_DIGITAL_CONTRAST
111 0x80, 0x80, 0x80,
112
113 1, 0x8F, // ENABLE SRGB OR DIGITAL CONTRAST
114 0x01, // CR8F
115
116 // 1, 0xA5, // disable spectrum modulation
C51 COMPILER V6.23a POST 09/10/2004 16:09:01 PAGE 3
117 // 0x00,
118 6, 0xA0,
119 #if PANEL_1280
0xD0, 0x00, 0xD0, 0x00, //CRA0-A3
0x30,//0x36,//0.6% //0x3f,//2% //CRA4
#else
123 0xE4, 0x00, 0xE4, 0x00, //CRA0-A3
124 0x32,//0x3A,//0.6% //0x3f,//2% //CRA4
125 #endif
126 #if NEW_SSC_HN
127 #if PANEL_1280
0x13, //CRA5 Turn-on Spread Specturm
#else
130 0x11, //CRA5 Turn-on Spread Specturm
131 #endif
132 #elif NEW_SSC_HO
#if PANEL_1280
0x47, //CRA5 Turn-on Spread Specturm
#else
0x45, //CRA5 Turn-on Spread Specturm
#endif
#else
0x47, //CRA5 Turn-on Spread Specturm
#endif
141
142 2, 0xA8, //FIFO START
143 0x08,0x80,
144
145
146 1,0x5f,
147 #if MVXPRL_HT17L
0x08,
#else
150 0x00, // the phase of output clock
151 #endif
152
153 //1,0xBE, //DVI POWER CONTROL
154 //0x60,
155
156
157
158 // high pass filter
159 5, 0x63,
160 0x04,0x20,0x00,0x00,0x40,
161 7, 0x69,
162 #if PANEL_1280
0x18,0x18,0xc8,0xff,0x10,0x00,0x00,
5, 0x71,
0x18,0x18,0xc8,0xff,0x10,
5, 0x78,
0x18,0x18,0xc8,0xff,0x10,
#else
169 0x10,0x10,0xc8,0xff,0x10,0x06,0x00,
170 5, 0x71,
171 0x10,0x08,0xc2,0xff,0x10,
172 5, 0x78,
173 0x10,0x10,0xc8,0xff,0x10,
174 #endif
175
176 // filter enable
177 1, 0x68,
178 #if HP_FILTER
C51 COMPILER V6.23a POST 09/10/2004 16:09:01 PAGE 4
0x2a,
#else
181 0x00,
182 #endif
183
184
185 -1 // EOT
186 };
187
188
189
190
191 //
192 // POST Initialization
193 //
194 void postInitMascot(void)
195 {
196 1 #if DEBUGMSG
printf("POST:\n");
#endif
199 1
200 1
201 1 #if (USE_TCON + USE_RSDS)
postTCONInit();
#endif
204 1
205 1 // Program POST init registers
206 1 #if DEBUGMSG
printf(" init Mosiac\n");
#endif
209 1 RegDataTableOut(postInitTable);
210 1
211 1 #if (USE_LVDS+USE_RSDS)
212 1 postLVDS_RSDSInit();
213 1 #endif
214 1
215 1 #if AU17_RSDS
postGammaInit(); //jordan0212
#endif
218 1
219 1 // Init and start Sync Processor
220 1 postStartSync();
221 1
222 1 }
223
224
225
226 // POST Start Sync Processor
227 void postStartSync(void)
228 {
229 1 unsigned char code sync_init0[] =
230 1 {
231 1 0x00, //CR08, disable Sync
232 1 VERRORRANGE, //CR09, Vsync error
233 1 HERRORRANGE //CR0A, Hsync error
234 1 };
235 1
236 1 unsigned char code sync_init1[] =
237 1 {
238 1 0x00,0x00,0x00, //CR00-02: clear status
239 1 0x00,0x36,0x00, //CR03-05: interrupt mask
240 1 0x00, //CR06
C51 COMPILER V6.23a POST 09/10/2004 16:09:01 PAGE 5
241 1 0x00 //CR07, separate sync
242 1 };
243 1
244 1 #if DEBUGMSG
printf(" sync start\n");
#endif
247 1
248 1 RegDataOut(0x08, sync_init0, 3);
249 1 RegDataOut(0x00, sync_init1, 8); //port A
250 1
251 1 RegByteOut(0x07, 0x14); //start Sync processor
252 1
253 1 }
254
255
256
257 #if (USE_LVDS+USE_RSDS)
258 void postLVDS_RSDSInit()
259 {
260 1
261 1 RegBitOut(0x2f, 0x00, 0x40); //Using RSDS or LVDS instead of Standard IO(4mA driving)
262 1
263 1 #if USE_RSDS
RegBitOut(0x58, 0x80, 0x80);
#endif
266 1
267 1 RegBitOut(0x2f, 0x00, 0x40);
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