post.c

采用台湾MRT晶捷公司的MRT4方案的液晶电视的程序

/************************************************
 *                                              *
 *      POST.C:  Power-up reset routine         *
 *                                              *
 ************************************************/

#include <reg51.h>
#include "mascot.h"
#include "osd.h"
#include "global.h"



//
//      Register table for POST init
//
unsigned char code postInitTable[] = {

    6, 0x25,
#if NEW_ADC
	0xFC,0x11,0x14,		//CR25-27
	0x00,0x10,0x1A,		//CR28-2A   	    
#else
	0xFC,0x10,0x12,		//CR25-27
	0x00,0x10,0x1A,		//CR28-2A
#endif 	
   	
    11, 0x12,			//CR12: ADC
	0x3A, 0x30,     	//R: OFFSET, COARSER, FINE
	0x3A, 0x30,     	//G: OFFSET, COARSER, FINE
	0x3A, 0x30,     	//B: OFFSET, COARSER, FINE
	0x02,			//CR18
	0xF2,			//CR19 VCO=10111010: Z=101(4K) Vco=11(100MHz/V)
	0xA0,			//CR1A DIVIDER: 1344
	0x48,			//CR1B: PhaseA
	0x94,			//HIDE THE RETRACE LINE

	1, 0x08,
	0x08,

	5, 0x2B,		//CR2B-2F: DCLK REGISTERS
	0x0C,		        //CR2B:  M Divier DCLK, 65M
	0x41,0x00,		//CR2C,CR2D Ndivider
	0x32,0x80,		//CR2E-2F 


	5, 0x20,		// Minify
	0x00, 0x00, 0x00, 0x00, //CR20-CR23
#if (USE_TCON + USE_RSDS)
	0x00,			//CR24
#else
	0xC0,			//CR24
#endif

	16, 0x30,				// Capture Interface
	0x03,					//CR30
	0x00,					//CR31
	0x07,					//CR32: -H/-V
	0x00,					//CR33
	0xA5,0x00,0x1D,0x00,	//CR34-37: Capture H/V Start
	0xFF,0x03,0xFF,0x02,	//CR38-3B: Capture Width/Height
	0xFF,					//CR3C: Capture FIFO Depth, width/4-1
	0x01,0x00,0x05,			//CR3D-3F: Clamp



#if PANEL_1280
	16, 0x40,                       // Display Interface
	0x60,							//CR40
	0xA8,0x9F,0xA2,0x26,			//CR41-CR44: Hort
	0x2A,0xFF,0x34,0x01,0x04,0x04, 	//CR45-4A: Vert
    0x00,0x00,0x00,0x00,            //CR4B-4E: H/V Zoom
	0x76,                      	 	//CR4F
#else
	16, 0x40,						//CR40-4E: Display Interface
	0x00,							//CR40
	0xA8,0x7F,0x82,0x11,			//CR41-CR44: Hort
	0x26,0xFF,0x23,0x03,0x03,0x86,	//CR45-4A: Vert
	0x00,0x00,0x00,0x00,			//CR4B-4E: H/V Zoom
	0x76,                       	//CR4F
#endif


	9, 0x50,				// Panel Interface
#if MVXPRL_HT17L
	0x86+(USE_GAMMA*8),     //CR50: TFT 18-bit double_pixel, dithering on 
	0x00,					//CR51
#elif (MVXPRL_CPT15R+AOC_CPTXG08_RSDS)
	0x47+(USE_GAMMA*8),     //CR50: TFT 18-bit single_pixel, dithering on 
	0x04,					//CR51
#elif (CPT_CLAA170EA03)
	0x46+(USE_GAMMA*8),     //CR50: TFT 18-bit double_pixel, dithering on 
	0x00,					//CR51
#elif (MVRL_SANYO15 + MVRL_NEC15)
	0x01+(USE_GAMMA*8),     //CR50: TFT 18-bit single_pixel, dithering off 
	0x04,					//CR51
#elif (MVPL_CMO17+MVRL_1920)
	0x80+(USE_GAMMA*8),     //CR50: TFT 24-bit double_pixel, dithering off 
	0x00,	
#else
	0x06+(USE_GAMMA*8),     //CR50: TFT 18-bit double_pixel, dithering on 
	0x00,					//CR51
#endif

	0x00,0x00,0x00,			//CR52-54: Contrast Adjustment
	0x00,0x00,0x00,			//CR55-57: Background Color
	0x00,					//CR58


	3, 0x80,                // USE_DIGITAL_CONTRAST
	0x80, 0x80, 0x80,

	1, 0x8F,				// ENABLE SRGB OR DIGITAL CONTRAST
	0x01,					// CR8F

//	1, 0xA5,		// disable spectrum modulation
//	0x00,
	6, 0xA0,
#if PANEL_1280
	0xD0, 0x00, 0xD0, 0x00, //CRA0-A3
	0x30,//0x36,//0.6% //0x3f,//2% //CRA4
#else
	0xE4, 0x00, 0xE4, 0x00, //CRA0-A3
	0x32,//0x3A,//0.6% //0x3f,//2% //CRA4
#endif
#if NEW_SSC_HN
#if PANEL_1280
	0x13,			//CRA5 Turn-on Spread Specturm
#else
	0x11,			//CRA5 Turn-on Spread Specturm
#endif
#elif NEW_SSC_HO
#if PANEL_1280
	0x47,			//CRA5 Turn-on Spread Specturm
#else
	0x45,			//CRA5 Turn-on Spread Specturm
#endif
#else
	0x47,			//CRA5 Turn-on Spread Specturm
#endif

	2, 0xA8,				//FIFO START
	0x08,0x80,


	1,0x5f,
#if MVXPRL_HT17L
	0x08,
#else	
	0x00,			// the phase of output clock
#endif

	//1,0xBE,			//DVI POWER CONTROL
	//0x60,



	// high pass filter
	5, 0x63,
	0x04,0x20,0x00,0x00,0x40,	
	7, 0x69,
#if PANEL_1280	
	0x18,0x18,0xc8,0xff,0x10,0x00,0x00,
	5, 0x71,
	0x18,0x18,0xc8,0xff,0x10,
	5, 0x78,
	0x18,0x18,0xc8,0xff,0x10,		
#else	
	0x10,0x10,0xc8,0xff,0x10,0x06,0x00,
	5, 0x71,
	0x10,0x08,0xc2,0xff,0x10,
	5, 0x78,
	0x10,0x10,0xc8,0xff,0x10,	
#endif

	// filter enable
	1, 0x68,
#if HP_FILTER
	0x2a,	
#else
	0x00,
#endif


	-1                              // EOT
};



 
//
//      POST Initialization
//
void postInitMascot(void)
{
#if DEBUGMSG
	printf("POST:\n");
#endif


#if (USE_TCON + USE_RSDS)
	postTCONInit();
#endif

	// Program POST init registers
#if DEBUGMSG
	printf("  init Mosiac\n");
#endif
	RegDataTableOut(postInitTable);

#if (USE_LVDS+USE_RSDS)
	postLVDS_RSDSInit();
#endif

#if AU17_RSDS
	postGammaInit(); //jordan0212
#endif

    // Init and start Sync Processor
	postStartSync();
    
}



//      POST Start Sync Processor
void postStartSync(void)
{
	unsigned char code sync_init0[] = 
	{
		0x00,           //CR08, disable Sync
		VERRORRANGE,	//CR09, Vsync error
		HERRORRANGE	//CR0A, Hsync error
	};
	
	unsigned char code sync_init1[] = 
	{
		0x00,0x00,0x00, //CR00-02: clear status
		0x00,0x36,0x00, //CR03-05: interrupt mask
		0x00,           //CR06
		0x00            //CR07, separate sync
	};

#if DEBUGMSG
	printf("  sync start\n");
#endif

	RegDataOut(0x08, sync_init0, 3);
	RegDataOut(0x00, sync_init1, 8);	//port A

	RegByteOut(0x07, 0x14);     		//start Sync processor

}



#if (USE_LVDS+USE_RSDS)
void postLVDS_RSDSInit()
{

	RegBitOut(0x2f, 0x00, 0x40);  //Using RSDS or LVDS instead of Standard IO(4mA driving)

#if USE_RSDS
	RegBitOut(0x58, 0x80, 0x80);
#endif

	RegBitOut(0x2f, 0x00, 0x40);

#if USE_LVDS
	RegByteOut(0x24, 0xC0);
#else
	RegByteOut(0x24, 0x80);
#endif

	RegByteOut(0xC0, 0x40); //Switch to TCN Register

#if USE_LVDS
	RegByteOut(0x6e, 0xf0); //Select register control for PLL in LVDS mode //LVDS also program 0x00 @_@?