📄 armperip.xml
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FIELD [14],[21:18] (NAME="Data Size", TYPE=tTCMSSize, ACCESS="R"),
SEPARATOR(TEXTNAME=", Instruction RAM: "),
FIELD [2],[9:6] (NAME="Instruction Size", TYPE=tTCMSSize, ACCESS="R")
}
</definition>
</displaytype>
<displaytype>
<name>XScale_PerformanceType0</name>
<requires></requires>
<definition>
TYPEDEF tXScaleEventType ENUM(WIDTH=8, DEFAULT="Reserved/unpredictable")
{
"Instruction cache miss" = 0,
"Instruction cache cannot deliver" = 1,
"Stall due to a data dependency" = 2,
"Instruction TLB miss" = 3,
"Data TLB miss" = 4,
"Branch instruction executed" = 5,
"Branch mispredicted" = 6,
"Instruction executed" = 7,
"Stall because data cache buffers are full" = 8,
"Stall because data cache buffers are full (contiguous)" = 9,
"Data cache access" = 10,
"Data cache miss" = 11,
"Data cache write-back" = 12,
"Software changed the PC." = 13,
"BCU received a new memory request" = 16,
"BCUs request queue is full" = 17,
"BCU queues were drained" = 18,
"BCU detected an ECC error" = 20,
"BCU detected a 1-bit error, while reading data from the bus" = 21,
"RMW cycle occurred due to narrow write" = 22
}
TYPEDEF tXScalePerformanceReporting ENUM(WIDTH=1, TOOLTIP="Enable generation of an interrupt when the counter passes through zero")
{
"No interrupt" = 0,
"Interrupt" = 1
}
TYPEDEF XScale_PerformanceType0(NAME="XScale Counter Event 0", CLASS="System") COMPOSITE(WIDTH=32)
{
FIELD[19:12] (NAME="Event", TYPE=tXScaleEventType),
SEPARATOR(GUINAME="NEWLINE", TEXTNAME=" ("),
SEPARATOR(GUINAME="Reporting:"),
FIELD[4] (NAME="Reporting", TYPE=tXScalePerformanceReporting, ACCESS="RW"),
SEPARATOR(TEXTNAME=")"),
FIELD[31:28],[11:7],[2:1] (NAME="", TYPE=RESERVED(WIDTH=11), ACCESS="0"),
FIELD[27:20],[6:3],[0] (NAME="", TYPE=RESERVED(WIDTH=13), ACCESS="V")
}
</definition>
</displaytype>
<displaytype>
<name>XScale_PerformanceType1</name>
<requires></requires>
<definition>
TYPEDEF tXScaleEventType ENUM(WIDTH=8, DEFAULT="Reserved/unpredictable")
{
"Instruction cache miss" = 0,
"Instruction cache cannot deliver" = 1,
"Stall due to a data dependency" = 2,
"Instruction TLB miss" = 3,
"Data TLB miss" = 4,
"Branch instruction executed" = 5,
"Branch mispredicted" = 6,
"Instruction executed" = 7,
"Stall because data cache buffers are full" = 8,
"Stall because data cache buffers are full (contiguous)" = 9,
"Data cache access" = 10,
"Data cache miss" = 11,
"Data cache write-back" = 12,
"Software changed the PC." = 13,
"BCU received a new memory request" = 16,
"BCUs request queue is full" = 17,
"BCU queues were drained" = 18,
"BCU detected an ECC error" = 20,
"BCU detected a 1-bit error, while reading data from the bus" = 21,
"RMW cycle occurred due to narrow write" = 22
}
TYPEDEF tXScalePerformanceReporting ENUM(WIDTH=1, TOOLTIP="Enable generation of an interrupt when the counter passes through zero")
{
"No interrupt" = 0,
"Interrupt" = 1
}
TYPEDEF XScale_PerformanceType1(NAME="XScale Counter Event 1", CLASS="System") COMPOSITE(WIDTH=32)
{
FIELD[27:20] (NAME="Event", TYPE=tXScaleEventType),
SEPARATOR(GUINAME="NEWLINE", TEXTNAME=" ("),
SEPARATOR(GUINAME="Reporting:"),
FIELD[4] (NAME="Reporting", TYPE=tXScalePerformanceReporting, ACCESS="RW"),
SEPARATOR(TEXTNAME=")"),
FIELD[31:28],[11:7],[2:1] (NAME="", TYPE=RESERVED(WIDTH=11), ACCESS="0"),
FIELD[19:12],[6:3],[0] (NAME="", TYPE=RESERVED(WIDTH=13), ACCESS="V")
}
</definition>
</displaytype>
<displaytype>
<name>XScale_PerformanceClock</name>
<requires></requires>
<definition>
TYPEDEF tXScaleCountEvery ENUM(WIDTH=1)
{
"1" = 0,
"64" = 1
}
TYPEDEF tXScalePerformanceReporting ENUM(WIDTH=1, TOOLTIP="Enable generation of an interrupt when the counter passes through zero")
{
"No interrupt" = 0,
"Interrupt" = 1
}
TYPEDEF XScale_PerformanceClock(NAME="XScale Clock Control", CLASS="System") COMPOSITE(WIDTH=32)
{
SEPARATOR(GUINAME="Clock count every", TEXTNAME="Every "),
FIELD[3] (NAME="Count every n cycles", TYPE=tXScaleCountEvery),
SEPARATOR(GUINAME="cycle(s)", TEXTNAME=" cycle(s)"),
SEPARATOR(GUINAME="NEWLINE", TEXTNAME=" ("),
SEPARATOR(GUINAME="Reporting:"),
FIELD[4] (NAME="Reporting", TYPE=tXScalePerformanceReporting, ACCESS="RW"),
SEPARATOR(TEXTNAME=")"),
FIELD[31:28],[11:7],[2:1] (NAME="", TYPE=RESERVED(WIDTH=11), ACCESS="0"),
FIELD[27:12],[6:3],[0] (NAME="", TYPE=RESERVED(WIDTH=21), ACCESS="V")
}
</definition>
</displaytype>
<displaytype>
<name>XScale_PerformanceControl</name>
<requires></requires>
<definition>
TYPEDEF XScale_PerformanceControl(NAME="XScale Performance Control", CLASS="System") COMPOSITE(WIDTH=32)
{
FIELD[31:28],[11],[7], [2:1] (NAME="", TYPE=RESERVED(WIDTH=8), ACCESS="0"),
FIELD[27:12], [3] (NAME="", TYPE=RESERVED(WIDTH=17), ACCESS="V"),
SEPARATOR(TEXTNAME="Enable:", GUINAME="Global enable"),
FIELD[0] (NAME="Global enable", TYPE=FLAG(SET="Y", UNSET="N"), ACCESS="RW"),
SEPARATOR(TEXTNAME=", Overflow:", GUINAME="NEWLINE"),
SEPARATOR(GUINAME=" "),
SEPARATOR(GUINAME="NEWLINE"),
GROUP(NAME="Overflowed")
{
SEPARATOR(GUINAME="Clock"),
FIELD[10] (NAME="Clock overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW"),
SEPARATOR(GUINAME="Event 0"),
FIELD[8] (NAME="Event 0 overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW"),
SEPARATOR(GUINAME="Event 1"),
FIELD[9] (NAME="Event 1 overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW")
},
SEPARATOR(TEXTNAME=", Interrupt:", GUINAME="NEWLINE"),
SEPARATOR(GUINAME=" "),
SEPARATOR(GUINAME="NEWLINE"),
GROUP(NAME="Interrupt enable")
{
SEPARATOR(GUINAME="Clock"),
FIELD[6] (NAME="Clock interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW"),
SEPARATOR(GUINAME="Event 0"),
FIELD[4] (NAME="Event 0 interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW"),
SEPARATOR(GUINAME="Event 1"),
FIELD[5] (NAME="Event 1 interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW")
},
SEPARATOR(GUINAME="NEWLINE"),
SEPARATOR(GUINAME=" "),
SEPARATOR(GUINAME="NEWLINE")
}
</definition>
</displaytype>
<displaytype>
<name>XScale_CPAccess</name>
<requires></requires>
<definition>
TYPEDEF tXScale_CPAccess13 ENUM(WIDTH=1)
{
"" = 0,
"CP13 " = 1
}
TYPEDEF tXScale_CPAccess12 ENUM(WIDTH=1)
{
"" = 0,
"CP12 " = 1
}
TYPEDEF tXScale_CPAccess11 ENUM(WIDTH=1)
{
"" = 0,
"CP11 " = 1
}
TYPEDEF tXScale_CPAccess10 ENUM(WIDTH=1)
{
"" = 0,
"CP10 " = 1
}
TYPEDEF tXScale_CPAccess9 ENUM(WIDTH=1)
{
"" = 0,
"CP9 " = 1
}
TYPEDEF tXScale_CPAccess8 ENUM(WIDTH=1)
{
"" = 0,
"CP8 " = 1
}
TYPEDEF tXScale_CPAccess7 ENUM(WIDTH=1)
{
"" = 0,
"CP7 " = 1
}
TYPEDEF tXScale_CPAccess6 ENUM(WIDTH=1)
{
"" = 0,
"CP6 " = 1
}
TYPEDEF tXScale_CPAccess5 ENUM(WIDTH=1)
{
"" = 0,
"CP5 " = 1
}
TYPEDEF tXScale_CPAccess4 ENUM(WIDTH=1)
{
"" = 0,
"CP4 " = 1
}
TYPEDEF tXScale_CPAccess3 ENUM(WIDTH=1)
{
"" = 0,
"CP3 " = 1
}
TYPEDEF tXScale_CPAccess2 ENUM(WIDTH=1)
{
"" = 0,
"CP2 " = 1
}
TYPEDEF tXScale_CPAccess1 ENUM(WIDTH=1)
{
"" = 0,
"CP1 " = 1
}
TYPEDEF tXScale_CPAccess0 ENUM(WIDTH=1)
{
"" = 0,
"CP0 " = 1
}
TYPEDEF XScale_CPAccess(NAME="Coprocessor Access", CLASS="System") COMPOSITE(WIDTH=32)
{
FIELD[31:14] (NAME="", TYPE=RESERVED(WIDTH=18), ACCESS="0"),
SEPARATOR(TEXTNAME="Access to: "),
FIELD[13] (NAME="Coprocessor 13", TYPE=tXScale_CPAccess13),
FIELD[12:8] (NAME="", TYPE=RESERVED(WIDTH=5), ACCESS="V"),
FIELD[7] (NAME="Coprocessor 7", TYPE=tXScale_CPAccess7),
FIELD[6] (NAME="Coprocessor 6", TYPE=tXScale_CPAccess6),
FIELD[5:1] (NAME="", TYPE=RESERVED(WIDTH=5), ACCESS="V"),
FIELD[0] (NAME="Accumulators", TYPE=tXScale_CPAccess0)
}
</definition>
</displaytype>
<displaytype>
<name>XScale_INTCTL</name>
<requires></requires>
<definition>
TYPEDEF XScale_INTCTL(NAME="XScale Interrupt Control", CLASS="System") COMPOSITE(WIDTH=32)
{
FIELD[31:4] (NAME="", TYPE=RESERVED(WIDTH=28), ACCESS="0"),
FIELD[3] (NAME="BCU Enable", TYPE=FLAG(SET="B", UNSET="b")),
FIELD[2] (NAME="PMU Enable", TYPE=FLAG(SET="P", UNSET="p")),
FIELD[1] (NAME="IRQ Enable", TYPE=FLAG(SET="I", UNSET="i")),
FIELD[0] (NAME="FIQ Enable", TYPE=FLAG(SET="F", UNSET="f"))
}
</definition>
</displaytype>
<displaytype>
<name>FPSID</name>
<requires></requires>
<definition>
TYPEDEF tImplementorVFP ENUM(WIDTH=8, DEFAULT="Unknown")
{
"ARM" = 0x41,
"Texas Instruments" = 0x54,
"Intel" = 0x69
}
TYPEDEF tFormatVFP ENUM(WIDTH=2)
{
"1" = 0,
"2" = 1,
"Reserved" = 2,
"Non-standard" = 3
}
TYPEDEF tPrecisionVFP ENUM(WIDTH=1)
{
"Single/Double" = 0,
"Single only" = 1
}
TYPEDEF tArchVFP ENUM(WIDTH=4, DEFAULT="Unknown")
{
"VFPv1" = 0,
"VFPv2" = 1
}
TYPEDEF FPSID(NAME="FPSID", CLASS="System") COMPOSITE(WIDTH=32)
{
FIELD[31:24] (NAME="Implementor", TYPE=tImplementorVFP, ACCESS="R"),
SEPARATOR(TEXTNAME=" "),
FIELD[19:16] (NAME="Arch", TYPE=tArchVFP, ACCESS="R"),
SEPARATOR(TEXTNAME=" "),
FIELD[20] (NAME="Precision", TYPE=tPrecisionVFP, ACCESS="R"),
SEPARATOR(TEXTNAME=" part "),
FIELD[15:8] (NAME="Part", TYPE=NUMERIC(WIDTH=8, DEFAULT="HEX"), ACCESS="R"),
SEPARATOR(TEXTNAME=" variant "),
FIELD[7:4] (NAME="Variant", TYPE=NUMERIC(WIDTH=4, DEFAULT="UDEC"), ACCESS="R"),
SEPARATOR(TEXTNAME=" revision "),
FIELD[3:0] (NAME="Architecture version", TYPE=NUMERIC(WIDTH=4, DEFAULT="UDEC"), ACCESS="R"),
SEPARATOR(TEXTNAME=" "),
FIELD[23] (NAME="HWSW", TYPE=FLAG(SET="SW", UNSET="HW"), ACCESS="R"),
SEPARATOR(TEXTNAME=" format "),
FIELD[22:21] (NAME="FMT", TYPE=tFormatVFP, ACCESS="R"),
SEPARATOR(TEXTNAME=" ")
}
</definition>
</displaytype>
<displaytype>
<name>FPEXC</name>
<requires></requires>
<definition>
TYPEDEF FPEXC(NAME="FPEXC", CLASS="System") COMPOSITE(WIDTH=32)
{
FIELD[31] (NAME="EX", TYPE=FLAG(SET="EX", UNSET="ex")),
SEPARATOR(TEXTNAME=" "),
FIELD[30] (NAME="Global enable", TYPE=FLAG(SET="EN", UNSET="en")),
SEPARATOR(TEXTNAME=" "),
FIELD[29:0] (NAME="Implementation defined", TYPE=NUMERIC(WIDTH=30, DEFAULT="HEX"))
}
</definition>
</displaytype>
<!-- Debug comms channel -->
<module>
<type>DCC_CP14</type>
<register>
<name>Control</name>
<bank>Debug Comms Channel</bank>
<description>Debug Comms Channel Control Register</description>
<cpreg cp="14" crn="0" crm="0" opcode_2="0"></cpreg>
<access>RO</access>
<width>32</width>
<display>DCC_Control</display>
</register>
<register>
<name>Read</name>
<bank>Debug Comms Channel</bank>
<description>Debug Comms Channel Read Register</description>
<cpreg cp="14" crn="1" crm="0" opcode_2="0"></cpreg>
<access>RO</access>
<width>32</width>
</register>
<register>
<name>Write</name>
<bank>Debug Comms Channel</bank>
<description>Debug Comms Channel Write Register</description>
<cpreg cp="14" crn="1" crm="0" opcode_2="0"></cpreg>
<access>WO</access>
<width>32</width>
</register>
</module>
<peripheral>
<name>DCC_CP14</name>
<component>
<name>DCC</name>
<type>DCC_CP14</type>
</component>
</peripheral>
<!-- FPA and FPE -->
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