prev_cmp_miaobiao.map.qmsg

verilog写的分频程序,可以对输入的频率分频

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 25 01:01:19 2008 " "Info: Processing started: Thu Sep 25 01:01:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off miaobiao -c miaobiao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off miaobiao -c miaobiao" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div.v" { { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.v" "" { Text "G:/tools/Quartus II/project/miaobiao/div.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "select.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file select.v" { { "Info" "ISGN_ENTITY_NAME" "1 select " "Info: Found entity 1: select" {  } { { "select.v" "" { Text "G:/tools/Quartus II/project/miaobiao/select.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "drv_dec.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file drv_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 drv_dec " "Info: Found entity 1: drv_dec" {  } { { "drv_dec.v" "" { Text "G:/tools/Quartus II/project/miaobiao/drv_dec.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "drv_cnt.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file drv_cnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 drv_cnt " "Info: Found entity 1: drv_cnt" {  } { { "drv_cnt.v" "" { Text "G:/tools/Quartus II/project/miaobiao/drv_cnt.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dtlatch.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dtlatch.v" { { "Info" "ISGN_ENTITY_NAME" "1 dtlatch " "Info: Found entity 1: dtlatch" {  } { { "dtlatch.v" "" { Text "G:/tools/Quartus II/project/miaobiao/dtlatch.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_dec.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file seg7_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 seg7_dec " "Info: Found entity 1: seg7_dec" {  } { { "seg7_dec.v" "" { Text "G:/tools/Quartus II/project/miaobiao/seg7_dec.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "oneshot.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file oneshot.v" { { "Info" "ISGN_ENTITY_NAME" "1 oneshot " "Info: Found entity 1: oneshot" {  } { { "oneshot.v" "" { Text "G:/tools/Quartus II/project/miaobiao/oneshot.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\";\";  expecting an identifier, or a number, or a system task, or \"(\", or \"\{\", or unary operator state.v(18) " "Error (10170): Verilog HDL syntax error at state.v(18) near text \";\";  expecting an identifier, or a number, or a system task, or \"(\", or \"\{\", or unary operator" {  } { { "state.v" "" { Text "G:/tools/Quartus II/project/miaobiao/state.v" 18 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\";\";  expecting an identifier, or a number, or a system task, or \"(\", or \"\{\", or unary operator state.v(24) " "Error (10170): Verilog HDL syntax error at state.v(24) near text \";\";  expecting an identifier, or a number, or a system task, or \"(\", or \"\{\", or unary operator" {  } { { "state.v" "" { Text "G:/tools/Quartus II/project/miaobiao/state.v" 24 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "state state.v(1) " "Error (10112): Ignored design unit \"state\" at state.v(1) due to previous errors" {  } { { "state.v" "" { Text "G:/tools/Quartus II/project/miaobiao/state.v" 1 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file state.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "151 " "Error: Peak virtual memory: 151 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Sep 25 01:01:20 2008 " "Error: Processing ended: Thu Sep 25 01:01:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}