div.v

verilog写的分频程序,可以对输入的频率分频

module div (clk,rst,q);
input clk,rst;
output q;
reg [6:0]data; 
reg q;

always @(posedge clk or negedge rst)
begin
       if (rst==0)
           begin 
                 data=7'b0;
                 q=1'b0;
           end
else 
           begin
             if(data<95)
             data=data+7'b1;
             else   
              begin 
                    q=~q;
                    data=7'b0;
              end
           end
end

endmodule