dtlatch.v.bak

来自「verilog写的分频程序,可以对输入的频率分频」· BAK 代码 · 共 29 行

module dtlatch(clk,en,rst,din,q);
input clk,en,rst;
input [15:0]din;
output [15:0]q;

reg [15:0]q;


always @(posedge clk or negedge rst)
begin
	if(rst==0)
	 q<=0;
	 else 
	 if(en==1)
	 q<=q;
	 else	
	 q[15:12]<=din[15:12];
	 q[11:8]<=din[11:8];
	 q[7:4]<=din[7:4];
	 q[3:0]<=din[3:0];
	 //else
	 //q<=q;
	 end
end

endmodule