oneshot.v

来自「verilog写的分频程序,可以对输入的频率分频」· Verilog 代码 · 共 19 行

module oneshot(clk,rst,swin,pulse);
input clk,rst,swin;
output pulse;
wire pulse;
reg s1,s2;

always @(posedge clk or negedge rst )
begin
	if (rst==0)
	begin
        s1<=1'b0;
        s2<=1'b0;
    end
    else  if(swin)
		s1<=swin;
		s2<=s1;
end
assign pulse=s1&(~s2);
endmodule