miaobiao.map.rpt

verilog写的分频程序,可以对输入的频率分频

Analysis & Synthesis report for miaobiao
Thu Sep 25 01:04:31 2008
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Failed - Thu Sep 25 01:04:31 2008            ;
; Quartus II Version          ; 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition ;
; Revision Name               ; miaobiao                                     ;
; Top-level Entity Name       ; div                                          ;
; Family                      ; MAX7000S                                     ;
+-----------------------------+----------------------------------------------+


+------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                  ;
+--------------------------------------------------------------+-----------------+---------------+
; Option                                                       ; Setting         ; Default Value ;
+--------------------------------------------------------------+-----------------+---------------+
; Device                                                       ; EPM7128SLC84-15 ;               ;
; Top-level entity name                                        ; div             ; miaobiao      ;
; Family name                                                  ; MAX7000S        ; Stratix II    ;
; Use Generated Physical Constraints File                      ; Off             ;               ;
; Use smart compilation                                        ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                          ; Off             ; Off           ;
; Preserve fewer node names                                    ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                    ; Off             ; Off           ;
; Verilog Version                                              ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                 ; VHDL93          ; VHDL93        ;
; State Machine Processing                                     ; Auto            ; Auto          ;
; Safe State Machine                                           ; Off             ; Off           ;
; Extract Verilog State Machines                               ; On              ; On            ;
; Extract VHDL State Machines                                  ; On              ; On            ;
; Ignore Verilog initial constructs                            ; Off             ; Off           ;
; Iteration limit for constant Verilog loops                   ; 5000            ; 5000          ;
; Iteration limit for non-constant Verilog loops               ; 250             ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                      ; On              ; On            ;
; Parallel Synthesis                                           ; Off             ; Off           ;
; NOT Gate Push-Back                                           ; On              ; On            ;
; Power-Up Don't Care                                          ; On              ; On            ;
; Remove Duplicate Registers                                   ; On              ; On            ;
; Ignore CARRY Buffers                                         ; Off             ; Off           ;
; Ignore CASCADE Buffers                                       ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                        ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                    ; Off             ; Off           ;
; Ignore LCELL Buffers                                         ; Auto            ; Auto          ;
; Ignore SOFT Buffers                                          ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                               ; Off             ; Off           ;
; Optimization Technique                                       ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                         ; On              ; On            ;
; Auto Logic Cell Insertion                                    ; On              ; On            ;
; Parallel Expander Chain Length                               ; 4               ; 4             ;
; Auto Parallel Expanders                                      ; On              ; On            ;
; Auto Open-Drain Pins                                         ; On              ; On            ;
; Auto Resource Sharing                                        ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell                                 ; 100             ; 100           ;
; Ignore translate_off and synthesis_off directives            ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report           ; On              ; On            ;
; HDL message level                                            ; Level2          ; Level2        ;
; Suppress Register Optimization Related Messages              ; Off             ; Off           ;
; Number of Removed Registers Reported in Synthesis Report     ; 100             ; 100           ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100             ; 100           ;
; Block Design Naming                                          ; Auto            ; Auto          ;
; Synthesis Effort                                             ; Auto            ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On              ; On            ;
+--------------------------------------------------------------+-----------------+---------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Sep 25 01:04:30 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off miaobiao -c miaobiao
Info: Found 1 design units, including 1 entities, in source file div.v
    Info: Found entity 1: div
Info: Found 1 design units, including 1 entities, in source file select.v
    Info: Found entity 1: select
Info: Found 1 design units, including 1 entities, in source file drv_dec.v
    Info: Found entity 1: drv_dec
Info: Found 1 design units, including 1 entities, in source file drv_cnt.v
    Info: Found entity 1: drv_cnt
Info: Found 1 design units, including 1 entities, in source file dtlatch.v
    Info: Found entity 1: dtlatch
Info: Found 1 design units, including 1 entities, in source file seg7_dec.v
    Info: Found entity 1: seg7_dec
Info: Found 1 design units, including 1 entities, in source file oneshot.v
    Info: Found entity 1: oneshot
Error (10170): Verilog HDL syntax error at state.v(18) near text ";";  expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator File: G:/tools/Quartus II/project/miaobiao/state.v Line: 18
Error (10170): Verilog HDL syntax error at state.v(24) near text ";";  expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator File: G:/tools/Quartus II/project/miaobiao/state.v Line: 24
Error (10112): Ignored design unit "state" at state.v(1) due to previous errors File: G:/tools/Quartus II/project/miaobiao/state.v Line: 1
Info: Found 0 design units, including 0 entities, in source file state.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
    Error: Peak virtual memory: 151 megabytes
    Error: Processing ended: Thu Sep 25 01:04:32 2008
    Error: Elapsed time: 00:00:02
    Error: Total CPU time (on all processors): 00:00:01