smpsadc.h

Mplab C30编译器

/********************************************************************/
/*              Header for SMPS ADC module library functions       */
/*******************************************************************/

#ifndef __SMPSADC_H
#define __SMPSADC_H


/* List of SFRs for ADC */
/* This list contains the SFRs with default (POR) values to be used for configuring ADC */
/* The user can modify this based on the requirement */

#define ADCON_VALUE						0x0000
#define ADPCFG_VALUE					0x0000
#define ADCPC0_VALUE					0x0000
#define ADCPC1_VALUE					0x0000
#define ADCPC2_VALUE					0x0000

/*----------------------------------------------------------------------------------------------------*/
/* ADCON Configuration Bit Definitions : */
/*----------------------------------------------------------------------------------------------------*/

#define ADC_MOD_EN						0x8000  /* A/D converter module Enabled */
#define ADC_MOD_DIS						0x0000  /* A/D converter module Enabled */

#define ADC_IDLE_DISCONT				0x2000  /* Discontinue device operation when device enters idle mode */
#define ADC_IDLE_CONT					0x0000  /* Continue device operation in idle mode */

#define ADC_SOFT_TRIG_EN				0x0400  /* Global software trigger must be cleared prior to initiating another trgger */
#define ADC_SOFT_TRIG_DIS				0x0000  /*When this bit is set by the user it will trigger conversions selected by 
											    /*the TRGSRC<4:0> bits in the ADCPCx register. */

#define ADC_DATA_FRA					0x0100  /*Fractional Data */
#define ADC_DATA_INT					0x0000  /*Integer Data */

#define ADC_INT_EN_1CONV				0x0080  /* Interrupt generated after 1st conversion is completed */
#define ADC_INT_EN_2CONV				0x0000  /* Interrupt generated after 2nd conversion is completed */

#define ADC_ORDER_ODD_FST				0x0040  /*ODD numbered Analog I/P 1st converted followes by EVEN numbered I/P */
#define ADC_ORDER_EVEN_FST				0x0000  /*EVEN numbered Analog I/P 1st converted followes by ODD numbered I/P */

#define ADC_SAMP_SEQ					0x0020  /* If Order=0 shared S&H sampled at start of 2nd Conversion.
								                   If Order=1 S&H sampled at start of 1st Conversion. */
#define ADC_SAMP_SIM					0x0000  /* Shared S&H sampled at the same time the dedicated S&H if shared S&H is not busy
												   If Shared S&H is busy at the time when dedicated S&H sampled, then shared S&H will sample 
												   at the start of new conversion */

#define ADC_PLL_EN_FADC_18				0x0007  /* A/D Conversion clock divider select if PLL Enabled */
#define ADC_PLL_EN_FADC_16				0x0006  /* A/D Conversion clock divider select if PLL Enabled */
#define ADC_PLL_EN_FADC_14				0x0005  /* A/D Conversion clock divider select if PLL Enabled */
#define ADC_PLL_EN_FADC_12				0x0004  /* A/D Conversion clock divider select if PLL Enabled */
#define ADC_PLL_EN_FADC_10				0x0003  /* A/D Conversion clock divider select if PLL Enabled */
#define ADC_PLL_EN_FADC_8				0x0002  /* A/D Conversion clock divider select if PLL Enabled */
#define ADC_PLL_EN_FADC_6				0x0001  /* A/D Conversion clock divider select if PLL Enabled */
#define ADC_PLL_EN_FADC_4				0x0000  /* A/D Conversion clock divider select if PLL Enabled */


#define ADC_PLL_DIS_FADC_18				0x0007  /* A/D Conversion clock divider select if PLL Disabled */
#define ADC_PLL_DIS_FADC_16				0x0006  /* A/D Conversion clock divider select if PLL Disabled */
#define ADC_PLL_DIS_FADC_14				0x0005  /* A/D Conversion clock divider select if PLL Disabled */
#define ADC_PLL_DIS_FADC_12				0x0004  /* A/D Conversion clock divider select if PLL Disabled */
#define ADC_PLL_DIS_FADC_10				0x0003  /* A/D Conversion clock divider select if PLL Disabled */
#define ADC_PLL_DIS_FADC_8				0x0002  /* A/D Conversion clock divider select if PLL Disabled */
#define ADC_PLL_DIS_FADC_6				0x0001  /* A/D Conversion clock divider select if PLL Disabled */
#define ADC_PLL_DIS_FADC_4				0x0000  /* A/D Conversion clock divider select if PLL Disabled */


/*----------------------------------------------------------------------------------------------------*/
/* ADPCFG Port Configuration Bit Definitions : */
/*----------------------------------------------------------------------------------------------------*/

#define ADC_PORT_PIN0_DIG				0x0001  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN0_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN1_DIG				0x0002  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN1_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN2_DIG				0x0004  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN2_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN3_DIG				0x0008  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN3_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN4_DIG				0x0010  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN4_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN5_DIG				0x0020  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN5_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN6_DIG				0x0040  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN6_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN7_DIG				0x0080  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN7_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN8_DIG				0x0100  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN8_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN9_DIG				0x0200  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN9_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN10_DIG				0x0400  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN10_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

#define ADC_PORT_PIN11_DIG				0x0800  /* Port pin in Digital mode, port read I/P enabled, A/D I/P mux connected to AVss */
#define ADC_PORT_PIN11_AN				0x0000  /* Port pin in Analog mode, port read I/P disabled A/D samples pin voltage*/

/*----------------------------------------------------------------------------------------------------*/
/* ADCPC0 Configuration Bit for Trigger source : */
/*----------------------------------------------------------------------------------------------------*/

#define ADC_AN3_2_IR_GEN_EN				0x8000  /* ADC Interrupt Request Enable for AN3 & AN2 */
#define ADC_AN3_2_IR_GEN_DIS			0x0000  /* ADC Interrupt Request Disable for AN3 & AN2 */


#define ADC_AN3_2_NOCONV				0x0000  /* No trigger Conversion Enabled for AN3 & AN2 */
#define ADC_AN3_2_TRIG_INDV_SW			0x0100  /* Individual software trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_GLB_SW			0x0200  /* Global software trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_PWM_SEVT			0x0300  /* PWM special event trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_PWM1				0x0400  /* PWM generator #1 trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_PWM2				0x0500  /* PWM generator #2 trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_PWM3				0x0600  /* PWM generator #3 trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_PWM4				0x0700  /* PWM generator #4 trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_TMR1				0x0C00  /* Timer #1 period match trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_TMR2				0x0D00  /* Timer #2 period match trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_CL_PWM1			0x0E00  /* PWM generator #1 current limit ADC trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_CL_PWM2			0x0F00  /* PWM generator #2 current limit ADC trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_CL_PWM3			0x1000  /* PWM generator #3 current limit ADC trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_CL_PWM4			0x1100  /* PWM generator #4 current limit ADC trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_FLT_PWM1			0x1600  /* PWM generator #1 fault ADC trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_FLT_PWM2			0x1700  /* PWM generator #2 fault ADC trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_FLT_PWM3			0x1800  /* PWM generator #3 fault ADC trigger selected for AN3 & AN2 */
#define ADC_AN3_2_TRIG_FLT_PWM4			0x1900  /* PWM generator #4 fault ADC trigger selected for AN3 & AN2 */


#define ADC_AN1_0_IR_GEN_EN				0x0080  /* ADC Interrupt Request Enable for AN1 & AN0 */
#define ADC_AN1_0_IR_GEN_DIS			0x0000  /* ADC Interrupt Request Disable for AN1 & AN0 */


#define ADC_AN1_0_NOCONV				0x0000  /* No trigger Conversion Enabled for AN1 & AN0 */
#define ADC_AN1_0_TRIG_INDV_SW			0x0001  /* Individual software trigger selected for AN1 & AN0 */
#define ADC_AN1_0_TRIG_GLB_SW			0x0002  /* Global software trigger selected for AN1 & AN0 */
#define ADC_AN1_0_TRIG_PWM_SEVT			0x0003  /* PWM special event trigger selected for AN1 & AN0 */
#define ADC_AN1_0_TRIG_PWM1				0x0004  /* PWM generator #1 trigger selected for AN1 & AN0 */