📄 smpspwm.h
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/**********************************************************************/
/* Header for SMPS PWM module library functions */
/*********************************************************************/
#ifndef __SMPSPWM_H
#define __SMPSPWM_H
/* List of SFRs for PWM */
/* This list contains the SFRs with default (POR) values to be used for configuring PWM */
/* The user can modify this based on the requirement */
#define PTCON_VALUE 0x0000
#define PTPER_VALUE 0x0000
#define MDC_VALUE 0x0000
#define SEVTCMP_VALUE 0x0000
#define PWMCON1_VALUE 0x0000
#define PWMCON2_VALUE 0x0000
#define PWMCON3_VALUE 0x0000
#define PWMCON4_VALUE 0x0000
#define PDC1_VALUE 0x0000
#define PDC2_VALUE 0x0000
#define PDC3_VALUE 0x0000
#define PDC4_VALUE 0x0000
#define PHASE1_VALUE 0x0000
#define PHASE2_VALUE 0x0000
#define PHASE3_VALUE 0x0000
#define PHASE4_VALUE 0x0000
#define DTR1_VALUE 0x0000
#define DTR2_VALUE 0x0000
#define DTR3_VALUE 0x0000
#define DTR4_VALUE 0x0000
#define ALTDTR1_VALUE 0x0000
#define ALTDTR2_VALUE 0x0000
#define ALTDTR3_VALUE 0x0000
#define ALTDTR4_VALUE 0x0000
#define TRGCON1_VALUE 0x0000
#define TRGCON2_VALUE 0x0000
#define TRGCON3_VALUE 0x0000
#define TRGCON4_VALUE 0x0000
#define IOCON1_VALUE 0x0000
#define IOCON2_VALUE 0x0000
#define IOCON3_VALUE 0x0000
#define IOCON4_VALUE 0x0000
#define FCLCON1_VALUE 0x0000
#define FCLCON2_VALUE 0x0000
#define FCLCON3_VALUE 0x0000
#define FCLCON4_VALUE 0x0000
#define TRIG1_VALUE 0x0000
#define TRIG2_VALUE 0x0000
#define TRIG3_VALUE 0x0000
#define TRIG4_VALUE 0x0000
#define LEBCON1_VALUE 0x0000
#define LEBCON2_VALUE 0x0000
#define LEBCON3_VALUE 0x0000
#define LEBCON4_VALUE 0x0000
/*----------------------------------------------------------------------------------------------------*/
/* PTCON Configuration Bit Definitions : */
/*----------------------------------------------------------------------------------------------------*/
#define PWM_MOD_EN 0x8000 /*PWM Module Enable */
#define PWM_MOD_DIS 0x0000 /*PWM Module Disable*/
#define PWM_IDLE_STOP 0x2000 /* PWM Time base in Idle mode Operation halts */
#define PWM_IDLE_CONT 0x0000 /* PWM Time base in Idle mode Operation runs */
#define PWM_SEVT_INT 0x0000 /* Special Event Interrupt Status bit */
#define PWM_SEVT_INT_EN 0x0800 /* Special Event Interrupt Enable */
#define PWM_SEVT_INT_DIS 0x0000 /* Special Event Interrupt Disable */
#define PWM_PER_UPDATE_IMM 0x0400 /* Enable Period Update Immediate */
#define PWM_PER_UPDATE_BOUND 0x0000 /* Enable Period Update on cycle Boundary */
#define PWM_SYNCPOL_LOW_ACT 0x0200 /* Input Polarity Synchronize Low active */
#define PWM_SYNCPOL_HIGH_ACT 0x0000 /* Input Polarity Synchronize Low active */
#define PWM_PTB_SYNC_EN 0x0100 /* Primary Time Base Sync Enable */
#define PWM_PTB_SYNC_DIS 0x0000 /* Primary Time Base Sync Disable */
#define PWM_EXT_PTB_SYNC_EN 0x0080 /* External Primary Time Base Sync Enable */
#define PWM_EXT_PTB_SYNC_DIS 0x0000 /* External Primary Time Base Sync Disable */
#define PWM_SYNC1 0x0000 /* Sync1 Source Selection */
#define PWM_SEVT_OP_SCALE1 0x0000 /* Special Event Trig Output Postscaler 1:1 */
#define PWM_SEVT_OP_SCALE2 0x0001 /* Special Event Trig Output Postscaler 1:2 */
#define PWM_SEVT_OP_SCALE3 0x0002 /* Special Event Trig Output Postscaler 1:3 */
#define PWM_SEVT_OP_SCALE4 0x0003 /* Special Event Trig Output Postscaler 1:4 */
#define PWM_SEVT_OP_SCALE5 0x0004 /* Special Event Trig Output Postscaler 1:5 */
#define PWM_SEVT_OP_SCALE6 0x0005 /* Special Event Trig Output Postscaler 1:6 */
#define PWM_SEVT_OP_SCALE7 0x0006 /* Special Event Trig Output Postscaler 1:7 */
#define PWM_SEVT_OP_SCALE8 0x0007 /* Special Event Trig Output Postscaler 1:8 */
#define PWM_SEVT_OP_SCALE9 0x0008 /* Special Event Trig Output Postscaler 1:9 */
#define PWM_SEVT_OP_SCALE10 0x0009 /* Special Event Trig Output Postscaler 1:10 */
#define PWM_SEVT_OP_SCALE11 0x000A /* Special Event Trig Output Postscaler 1:11 */
#define PWM_SEVT_OP_SCALE12 0x000B /* Special Event Trig Output Postscaler 1:12 */
#define PWM_SEVT_OP_SCALE13 0x000C /* Special Event Trig Output Postscaler 1:13 */
#define PWM_SEVT_OP_SCALE14 0x000D /* Special Event Trig Output Postscaler 1:14 */
#define PWM_SEVT_OP_SCALE15 0x000E /* Special Event Trig Output Postscaler 1:15 */
#define PWM_SEVT_OP_SCALE16 0x000F /* Special Event Trig Output Postscaler 1:16 */
/*----------------------------------------------------------------------------------------------------*/
/* PWMCON1 Configuration Bit Definitions : */
/*----------------------------------------------------------------------------------------------------*/
#define PWM1_FLT_INT_STAT 0x0000 /* Fault Interrupt Status software cleared */
#define PWM1_CL_INT_STAT 0x0000 /* Current Limit Interrupt Status software cleared */
#define PWM1_TRG_INT_STAT 0x0000 /* Trigger Interrupt Status software cleared */
#define PWM1_FLT_INT_EN 0x1000 /* PWM1 Fault Interrupt Enable */
#define PWM1_FLT_INT_DIS 0x0000 /* PWM1 Fault Interrupt Disable */
#define PWM1_CL_INT_EN 0x0800 /* PWM1 Current Limit Interrupt Enable */
#define PWM1_CL_INT_DIS 0x0000 /* PWM1 Current Limit Interrupt Disable */
#define PWM1_TRG_INT_EN 0x0400 /* PWM1 Trigger Interrupt Enable */
#define PWM1_TRG_INT_DIS 0x0000 /* PWM1 Trigger Interrupt Disable */
#define PWM1_TB_MODE_PH1 0x0200 /* Phase1 reg provides Time base period for PWM Gen */
#define PWM1_TB_MODE_PTB 0x0000 /* Primary time base provides timing for PWM Gen */
#define PWM1_D_CYLE_MDC 0x0100 /* Master Duty Cycle reg provides duty cycle info for PWM Gen */
#define PWM1_D_CYLE_DC1 0x0000 /* Duty Cycle1 reg provides duty cycle info for PWM Gen */
#define PWM1_DT_POS 0x0000 /* Positive dead time applied to all o/p modes */
#define PWM1_DT_NEG 0x0040 /* Negative dead time applied to all o/p modes */
#define PWM1_DT_DIS 0x0080 /* Dead time function disabled */
#define PWM1_CL_RES_TB_EN 0x0002 /* Current Limit source resets time base for this PWM gen in independent time base mode */
#define PWM1_EXT_RES_DIS 0x0000 /* External pins do not affect PWM time base */
#define PWM1_PDC_UPDATE_IMM 0x0001 /* Updates to active PDC regs are immediate */
#define PWM1_PDC_UPDATE_SYNC 0x0000 /* Updates to active PDC regs are sync with PWM time base */
/*----------------------------------------------------------------------------------------------------*/
/* PWMCON2 Configuration Bit Definitions : */
/*----------------------------------------------------------------------------------------------------*/
#define PWM2_FLT_INT_STAT 0x0000 /* Fault Interrupt Status software cleared */
#define PWM2_CL_INT_STAT 0x0000 /* Current Limit Interrupt Status software cleared */
#define PWM2_TRG_INT_STAT 0x0000 /* Trigger Interrupt Status software cleared */
#define PWM2_FLT_INT_EN 0x1000 /* PWM2 Fault Interrupt Enable */
#define PWM2_FLT_INT_DIS 0x0000 /* PWM2 Fault Interrupt Disable */
#define PWM2_CL_INT_EN 0x0800 /* PWM2 Current Limit Interrupt Enable */
#define PWM2_CL_INT_DIS 0x0000 /* PWM2 Current Limit Interrupt Disable */
#define PWM2_TRG_INT_EN 0x0400 /* PWM2 Trigger Interrupt Enable */
#define PWM2_TRG_INT_DIS 0x0000 /* PWM2 Trigger Interrupt Disable */
#define PWM2_TB_MODE_PH2 0x0200 /* Phase2 reg provides Time base period for PWM Gen */
#define PWM2_TB_MODE_PTB 0x0000 /* Primary time base provides timing for PWM Gen */
#define PWM2_D_CYLE_MDC 0x0100 /* Master Duty Cycle reg provides duty cycle info for PWM Gen */
#define PWM2_D_CYLE_DC2 0x0000 /* Duty Cycle2 reg provides duty cycle info for PWM Gen */
#define PWM2_DT_POS 0x0000 /* Positive dead time applied to all o/p modes */
#define PWM2_DT_NEG 0x0040 /* Negative dead time applied to all o/p modes */
#define PWM2_DT_DIS 0x0080 /* Dead time function disabled */
#define PWM2_CL_RES_TB_EN 0x0002 /* Current Limit source resets time base for this PWM gen in independent time base mode */
#define PWM2_EXT_RES_DIS 0x0000 /* External pins do not affect PWM time base */
#define PWM2_PDC_UPDATE_IMM 0x0001 /* Updates to active PDC regs are immediate */
#define PWM2_PDC_UPDATE_SYNC 0x0000 /* Updates to active PDC regs are sync with PWM time base */
/*----------------------------------------------------------------------------------------------------*/
/* PWMCON3 Configuration Bit Definitions : */
/*----------------------------------------------------------------------------------------------------*/
#define PWM3_FLT_INT_STAT 0x0000 /* Fault Interrupt Status software cleared */
#define PWM3_CL_INT_STAT 0x0000 /* Current Limit Interrupt Status software cleared */
#define PWM3_TRG_INT_STAT 0x0000 /* Trigger Interrupt Status software cleared */
#define PWM3_FLT_INT_EN 0x1000 /* PWM3 Fault Interrupt Enable */
#define PWM3_FLT_INT_DIS 0x0000 /* PWM3 Fault Interrupt Disable */
#define PWM3_CL_INT_EN 0x0800 /* PWM3 Current Limit Interrupt Enable */
#define PWM3_CL_INT_DIS 0x0000 /* PWM3 Current Limit Interrupt Disable */
#define PWM3_TRG_INT_EN 0x0400 /* PWM3 Trigger Interrupt Enable */
#define PWM3_TRG_INT_DIS 0x0000 /* PWM3 Trigger Interrupt Disable */
#define PWM3_TB_MODE_PH3 0x0200 /* Phase3 reg provides Time base period for PWM Gen */
#define PWM3_TB_MODE_PTB 0x0000 /* Primary time base provides timing for PWM Gen */
#define PWM3_D_CYLE_MDC 0x0100 /* Master Duty Cycle reg provides duty cycle info for PWM Gen */
#define PWM3_D_CYLE_DC3 0x0000 /* Duty Cycle3 reg provides duty cycle info for PWM Gen */
#define PWM3_DT_POS 0x0000 /* Positive dead time applied to all o/p modes */
#define PWM3_DT_NEG 0x0040 /* Negative dead time applied to all o/p modes */
#define PWM3_DT_DIS 0x0080 /* Dead time function disabled */
#define PWM3_CL_RES_TB_EN 0x0002 /* Current Limit source resets time base for this PWM gen in independent time base mode */
#define PWM3_EXT_RES_DIS 0x0000 /* External pins do not affect PWM time base */
#define PWM3_PDC_UPDATE_IMM 0x0001 /* Updates to active PDC regs are immediate */
#define PWM3_PDC_UPDATE_SYNC 0x0000 /* Updates to active PDC regs are sync with PWM time base */
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