adc.h

Mplab C30编译器

#define ADC_CONV_CLK_30Tcy          0xFFFB
#define ADC_CONV_CLK_59Tcy2         0xFFFA
#define ADC_CONV_CLK_29Tcy          0xFFF9
#define ADC_CONV_CLK_57Tcy2         0xFFF8
#define ADC_CONV_CLK_28Tcy          0xFFF7
#define ADC_CONV_CLK_55Tcy2         0xFFF6
#define ADC_CONV_CLK_27Tcy          0xFFF5
#define ADC_CONV_CLK_53Tcy2         0xFFF4
#define ADC_CONV_CLK_26Tcy          0xFFF3
#define ADC_CONV_CLK_51Tcy2         0xFFF2
#define ADC_CONV_CLK_25Tcy          0xFFF1
#define ADC_CONV_CLK_49Tcy2         0xFFF0
#define ADC_CONV_CLK_24Tcy          0xFFEF
#define ADC_CONV_CLK_47Tcy2         0xFFEE
#define ADC_CONV_CLK_23Tcy          0xFFED
#define ADC_CONV_CLK_45Tcy2         0xFFEC
#define ADC_CONV_CLK_22Tcy          0xFFEB
#define ADC_CONV_CLK_43Tcy2         0xFFEA
#define ADC_CONV_CLK_21Tcy          0xFFE9
#define ADC_CONV_CLK_41Tcy2         0xFFE8
#define ADC_CONV_CLK_20Tcy          0xFFE7
#define ADC_CONV_CLK_39Tcy2         0xFFE6
#define ADC_CONV_CLK_19Tcy          0xFFE5
#define ADC_CONV_CLK_37Tcy2         0xFFE4
#define ADC_CONV_CLK_18Tcy          0xFFE3
#define ADC_CONV_CLK_35Tcy2         0xFFE2
#define ADC_CONV_CLK_17Tcy          0xFFE1
#define ADC_CONV_CLK_33Tcy2         0xFFE0
#define ADC_CONV_CLK_16Tcy          0xFFDF
#define ADC_CONV_CLK_31Tcy2         0xFFDE
#define ADC_CONV_CLK_15Tcy          0xFFDD
#define ADC_CONV_CLK_29Tcy2         0xFFDC
#define ADC_CONV_CLK_14Tcy          0xFFDB
#define ADC_CONV_CLK_27Tcy2         0xFFDA
#define ADC_CONV_CLK_13Tcy          0xFFD9
#define ADC_CONV_CLK_25Tcy2         0xFFD8
#define ADC_CONV_CLK_12Tcy          0xFFD7
#define ADC_CONV_CLK_23Tcy2         0xFFD6
#define ADC_CONV_CLK_11Tcy          0xFFD5
#define ADC_CONV_CLK_21Tcy2         0xFFD4
#define ADC_CONV_CLK_10Tcy          0xFFD3
#define ADC_CONV_CLK_19Tcy2         0xFFD2
#define ADC_CONV_CLK_9Tcy           0xFFD1
#define ADC_CONV_CLK_17Tcy2         0xFFD0
#define ADC_CONV_CLK_8Tcy           0xFFCF
#define ADC_CONV_CLK_15Tcy2         0xFFCE
#define ADC_CONV_CLK_7Tcy           0xFFCD
#define ADC_CONV_CLK_13Tcy2         0xFFCC
#define ADC_CONV_CLK_6Tcy           0xFFCB
#define ADC_CONV_CLK_11Tcy2         0xFFCA
#define ADC_CONV_CLK_5Tcy           0xFFC9
#define ADC_CONV_CLK_9Tcy2          0xFFC8
#define ADC_CONV_CLK_4Tcy           0xFFC7
#define ADC_CONV_CLK_7Tcy2          0xFFC6
#define ADC_CONV_CLK_3Tcy           0xFFC5
#define ADC_CONV_CLK_5Tcy2          0xFFC4
#define ADC_CONV_CLK_2Tcy           0xFFC3
#define ADC_CONV_CLK_3Tcy2          0xFFC2
#define ADC_CONV_CLK_Tcy            0xFFC1  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_Tcy2           0xFFC0  /* A/D Conversion Clock Select bits */

/* ADxCON4 register */

#define ADC_DMA_BUF_LOC_128         0xFFFF /* Allocates words of buffer to each analog input */
#define ADC_DMA_BUF_LOC_64          0xFFFE /* Allocates words of buffer to each analog input */
#define ADC_DMA_BUF_LOC_32          0xFFFD /* Allocates words of buffer to each analog input */
#define ADC_DMA_BUF_LOC_16          0xFFFC /* Allocates words of buffer to each analog input */
#define ADC_DMA_BUF_LOC_8           0xFFFB /* Allocates words of buffer to each analog input */
#define ADC_DMA_BUF_LOC_4           0xFFFA /* Allocates words of buffer to each analog input */
#define ADC_DMA_BUF_LOC_2           0xFFF9 /* Allocates words of buffer to each analog input */
#define ADC_DMA_BUF_LOC_1           0xFFF8 /* Allocates words of buffer to each analog input */

/* ADCx Input CHANNEL 1,2,3 select register (ADxCHS123) configuration defines */

#define ADC_CH123_NEG_SAMPLEB_9_10_11  0xFFFF /* A/D CH1 neg i/p is AN9 , CH2 neg i/p is AN10, CH3 neg i/p is AN11*/
#define ADC_CH123_NEG_SAMPLEB_6_7_8    0xFDFF /* A/D CH1 neg i/p is AN6 , CH2 neg i/p is AN7, CH3 neg i/p is AN8*/
#define ADC_CH123_NEG_SAMPLEB_VREFN    0xF9FF /* A/D CH1 , CH2 and CH3 neg i/p is Vref-*/

#define ADC_CH123_POS_SAMPLEB_3_4_5    0xFFFF /* A/D CH1 pos i/p is AN3, CH2 pos i/p is AN4, CH3 pos i/p is AN5*/
#define ADC_CH123_POS_SAMPLEB_0_1_2    0xFEFF /* A/D CH1 pos i/p is AN0, CH2 pos i/p is AN1, CH3 pos i/p is AN2*/

#define ADC_CH123_NEG_SAMPLEA_9_10_11  0xFFFF /* A/D CH1 neg i/p is AN9 , CH2 neg i/p is AN10, CH3 neg i/p is AN11*/
#define ADC_CH123_NEG_SAMPLEA_6_7_8    0xFFFD /* A/D CH1 neg i/p is AN6 , CH2 neg i/p is AN7, CH3 neg i/p is AN8*/
#define ADC_CH123_NEG_SAMPLEA_VREFN    0xFFF9 /* A/D CH1 , CH2 and CH3 neg i/p is Vref-*/

#define ADC_CH123_POS_SAMPLEA_3_4_5    0xFFFF /* A/D CH1 pos i/p is AN3, CH2 pos i/p is AN4, CH3 pos i/p is AN5*/
#define ADC_CH123_POS_SAMPLEA_0_1_2    0xFFFE /* A/D CH1 pos i/p is AN0, CH2 pos i/p is AN1, CH3 pos i/p is AN2*/

/* ADCx Input channel 0 select register */

#define ADC_CH0_NEG_SAMPLEB_AN1     0xFFFF /* CH0 negative input is AN1 */
#define ADC_CH0_NEG_SAMPLEB_VREFN   0x7FFF /* CH0 negative input is VREF- */

#define ADC_CH0_POS_SAMPLEB_AN31    0xFFFF /* A/D CH0 pos i/p sel for SAMPLE B is AN31 */
#define ADC_CH0_POS_SAMPLEB_AN30    0xFEFF /* A/D CH0 pos i/p sel for SAMPLE B is AN30 */
#define ADC_CH0_POS_SAMPLEB_AN29    0xFDFF /* A/D CH0 pos i/p sel for SAMPLE B is AN29 */
#define ADC_CH0_POS_SAMPLEB_AN28    0xFCFF /* A/D CH0 pos i/p sel for SAMPLE B is AN28 */
#define ADC_CH0_POS_SAMPLEB_AN27    0xFBFF /* A/D CH0 pos i/p sel for SAMPLE B is AN27 */
#define ADC_CH0_POS_SAMPLEB_AN26    0xFAFF /* A/D CH0 pos i/p sel for SAMPLE B is AN26 */
#define ADC_CH0_POS_SAMPLEB_AN25    0xF9FF /* A/D CH0 pos i/p sel for SAMPLE B is AN25 */
#define ADC_CH0_POS_SAMPLEB_AN24    0xF8FF /* A/D CH0 pos i/p sel for SAMPLE B is AN24 */
#define ADC_CH0_POS_SAMPLEB_AN23    0xF7FF /* A/D CH0 pos i/p sel for SAMPLE B is AN23 */
#define ADC_CH0_POS_SAMPLEB_AN22    0xF6FF /* A/D CH0 pos i/p sel for SAMPLE B is AN22 */
#define ADC_CH0_POS_SAMPLEB_AN21    0xF5FF /* A/D CH0 pos i/p sel for SAMPLE B is AN21 */
#define ADC_CH0_POS_SAMPLEB_AN20    0xF4FF /* A/D CH0 pos i/p sel for SAMPLE B is AN20 */
#define ADC_CH0_POS_SAMPLEB_AN19    0xF3FF /* A/D CH0 pos i/p sel for SAMPLE B is AN19 */
#define ADC_CH0_POS_SAMPLEB_AN18    0xF2FF /* A/D CH0 pos i/p sel for SAMPLE B is AN18 */
#define ADC_CH0_POS_SAMPLEB_AN17    0xF1FF /* A/D CH0 pos i/p sel for SAMPLE B is AN17 */
#define ADC_CH0_POS_SAMPLEB_AN16    0xF0FF /* A/D CH0 pos i/p sel for SAMPLE B is AN16 */
#define ADC_CH0_POS_SAMPLEB_AN15    0xEFFF /* A/D CH0 pos i/p sel for SAMPLE B is AN15 */
#define ADC_CH0_POS_SAMPLEB_AN14    0xEEFF /* A/D CH0 pos i/p sel for SAMPLE B is AN14 */
#define ADC_CH0_POS_SAMPLEB_AN13    0xEDFF /* A/D CH0 pos i/p sel for SAMPLE B is AN13 */
#define ADC_CH0_POS_SAMPLEB_AN12    0xECFF /* A/D CH0 pos i/p sel for SAMPLE B is AN12 */
#define ADC_CH0_POS_SAMPLEB_AN11    0xEBFF /* A/D CH0 pos i/p sel for SAMPLE B is AN11 */
#define ADC_CH0_POS_SAMPLEB_AN10    0xEAFF /* A/D CH0 pos i/p sel for SAMPLE B is AN10 */
#define ADC_CH0_POS_SAMPLEB_AN9     0xE9FF /* A/D CH0 pos i/p sel for SAMPLE B is AN9 */
#define ADC_CH0_POS_SAMPLEB_AN8     0xE8FF /* A/D CH0 pos i/p sel for SAMPLE B is AN8 */
#define ADC_CH0_POS_SAMPLEB_AN7     0xE7FF /* A/D CH0 pos i/p sel for SAMPLE B is AN7 */
#define ADC_CH0_POS_SAMPLEB_AN6     0xE6FF /* A/D CH0 pos i/p sel for SAMPLE B is AN6 */
#define ADC_CH0_POS_SAMPLEB_AN5     0xE5FF /* A/D CH0 pos i/p sel for SAMPLE B is AN5 */
#define ADC_CH0_POS_SAMPLEB_AN4     0xE4FF /* A/D CH0 pos i/p sel for SAMPLE B is AN4 */
#define ADC_CH0_POS_SAMPLEB_AN3     0xE3FF /* A/D CH0 pos i/p sel for SAMPLE B is AN3 */
#define ADC_CH0_POS_SAMPLEB_AN2     0xE2FF /* A/D CH0 pos i/p sel for SAMPLE B is AN2 */
#define ADC_CH0_POS_SAMPLEB_AN1     0xE1FF /* A/D CH0 pos i/p sel for SAMPLE B is AN1 */
#define ADC_CH0_POS_SAMPLEB_AN0     0xE0FF /* A/D CH0 pos i/p sel for SAMPLE B is AN0 */

#define ADC_CH0_NEG_SAMPLEA_AN1     0xFFFF /*A/D CH0 neg I/P sel for SAMPLE A is AN1 */
#define ADC_CH0_NEG_SAMPLEA_VREFN   0xFF7F /*A/D CH0 neg I/P sel for SAMPLE A is Vrefn */

#define ADC_CH0_POS_SAMPLEA_AN31    0xFFFF  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN31 */
#define ADC_CH0_POS_SAMPLEA_AN30    0xFFFE  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN30 */
#define ADC_CH0_POS_SAMPLEA_AN29    0xFFFD  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN29 */
#define ADC_CH0_POS_SAMPLEA_AN28    0xFFFC  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN28 */
#define ADC_CH0_POS_SAMPLEA_AN27    0xFFFB  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN27 */
#define ADC_CH0_POS_SAMPLEA_AN26    0xFFFA  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN26 */
#define ADC_CH0_POS_SAMPLEA_AN25    0xFFF9  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN25 */   
#define ADC_CH0_POS_SAMPLEA_AN24    0xFFF8  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN24 */   
#define ADC_CH0_POS_SAMPLEA_AN23    0xFFF7  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN23 */ 
#define ADC_CH0_POS_SAMPLEA_AN22    0xFFF6  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN22 */   
#define ADC_CH0_POS_SAMPLEA_AN21    0xFFF5  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN21 */   
#define ADC_CH0_POS_SAMPLEA_AN20    0xFFF4  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN20 */   
#define ADC_CH0_POS_SAMPLEA_AN19    0xFFF3  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN19 */   
#define ADC_CH0_POS_SAMPLEA_AN18    0xFFF2  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN18 */   
#define ADC_CH0_POS_SAMPLEA_AN17    0xFFF1  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN17 */   
#define ADC_CH0_POS_SAMPLEA_AN16    0xFFF0  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN16 */   
#define ADC_CH0_POS_SAMPLEA_AN15    0xFFEF  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN15 */
#define ADC_CH0_POS_SAMPLEA_AN14    0xFFEE  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN14 */
#define ADC_CH0_POS_SAMPLEA_AN13    0xFFED  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN13 */
#define ADC_CH0_POS_SAMPLEA_AN12    0xFFEC  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN12 */
#define ADC_CH0_POS_SAMPLEA_AN11    0xFFEB  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN11 */
#define ADC_CH0_POS_SAMPLEA_AN10    0xFFEA  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN10 */
#define ADC_CH0_POS_SAMPLEA_AN9     0xFFE9  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN9 */   
#define ADC_CH0_POS_SAMPLEA_AN8     0xFFE8  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN8 */   
#define ADC_CH0_POS_SAMPLEA_AN7     0xFFE7  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN7 */ 
#define ADC_CH0_POS_SAMPLEA_AN6     0xFFE6  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN6 */   
#define ADC_CH0_POS_SAMPLEA_AN5     0xFFE5  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN5 */   
#define ADC_CH0_POS_SAMPLEA_AN4     0xFFE4  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN4 */   
#define ADC_CH0_POS_SAMPLEA_AN3     0xFFE3  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN3 */   
#define ADC_CH0_POS_SAMPLEA_AN2     0xFFE2  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN2 */   
#define ADC_CH0_POS_SAMPLEA_AN1     0xFFE1  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN1 */   
#define ADC_CH0_POS_SAMPLEA_AN0     0xFFE0  /* A/D Chan 0 pos i/p sel for SAMPLE A is AN0 */   

#define ADC_RESULT_FIRST                0x0000  /* A/D read results from start of DMA buffer */
#define ADC_RESULT_SECOND               0x0008  /* A/D read results from middle of DMA buffer */

/*defines for ADxCSSL register */

#define SKIP_SCAN_AN0                   0xFFFE /*Skip AN0 for Input Scan */
#define SKIP_SCAN_AN1                   0xFFFD /*Skip AN1 for Input Scan */    
#define SKIP_SCAN_AN2                   0xFFFB /*Skip AN2 for Input Scan */
#define SKIP_SCAN_AN3                   0xFFF7 /*Skip AN3 for Input Scan */