adc.h

Mplab C30编译器

/********************************************************************/
/*              Header for 12 bit ADC module library functions      */
/*                      for 33F/ 24H devices only                   */
/********************************************************************/

#if defined(__dsPIC33F__)
#include <p33Fxxxx.h>
#elif defined(__PIC24H__)
#include <p24Hxxxx.h>
#else
#error "Does not build on this target"
#endif

#ifndef __ADC_H
#define __ADC_H

/* List of SFRs for ADC */
/* This list contains the SFRs with default (POR) values to be used for configuring ADC */
/* The user can modify this based on the requirement */

#define AD1CON1_VALUE                0x0000
#define AD1CON2_VALUE                0x0000
#define AD1CON3_VALUE                0x0000
#define AD1CON4_VALUE                0x0000
#define AD1CHS123_VALUE              0x0000
#define AD1CH0_VALUE                 0x0000
#define AD1CHSS_VALUE                0x0000
#define AD1CSSL_VALUE                0x0000
#define AD1PCFGH_VALUE               0x0000
#define AD1PCFGL_VALUE               0x0000

#ifdef _AD2IF

#define AD2CON1_VALUE                0x0000
#define AD2CON2_VALUE                0x0000
#define AD2CON3_VALUE                0x0000
#define AD2CON4_VALUE                0x0000
#define AD2CHS123_VALUE              0x0000
#define AD2CH0_VALUE                 0x0000
#define AD2CHSS_VALUE                0x0000
#define AD2CSSL_VALUE                0x0000
#define AD2PCFGH_VALUE               0x0000
#define AD2PCFGL_VALUE               0x0000

#endif

/* AD1CON1 Configuration Bit Definitions */

#define ADC_MODULE_ON               0xFFFF /* A/D Converter on */
#define ADC_MODULE_OFF              0x7FFF /* A/D Converter off */

#define ADC_IDLE_CONTINUE           0xDFFF /* A/D Operate in Idle mode */
#define ADC_IDLE_STOP               0xFFFF /* A/D Stop in Idle mode */

#define ADC_ADDMABM_ORDER           0XFFFF /*DMA buffers are written in the order of conversion */
#define ADC_ADDMABM_SCATTR          0xEFFF /* DMA buffers are written in Scatter/Gather mode */

#define ADC_AD12B_12BIT             0xFFFF /* 12 bit, 1-channel ADC operation */
#define ADC_AD12B_10BIT             0xFBFF /* 10 bit, 4-channel ADC operation */

#define ADC_FORMAT_SIGN_FRACT       0xFFFF /* A/D data format signed fractional */
#define ADC_FORMAT_FRACT            0xFEFF /* A/D data format fractional */
#define ADC_FORMAT_SIGN_INT         0xFDFF /* A/D data format signed integer */
#define ADC_FORMAT_INTG             0xFCFF /* A/D data format integer */

/* SSRC<2:0> bit defines */

#define ADC_CLK_AUTO                0xFFFF /* Internal counter ends sampling and starts conversion (Auto convert) */
#define ADC_CLK_MPWM                0xFF7F /* MPWM interval ends sampling and starts conversion */
#define ADC_CLK_TMR                 0xFF5F /* GP Timer compare ends sampling and starts conversion */
#define ADC_CLK_INT0                0xFF3F /* Active transition on INTx ends sampling and starts conversion */
#define ADC_CLK_MANUAL              0xFF1F /* Clearing sample (SAMP) bit ends sampling and starts conversion */

#define ADC_SIMULTANEOUS            0xFFFF /* Simultaneous sampling of CH0, CH1, CH2 and CH3 based on CHPS and AD12B bits*/
#define ADC_MULTIPLE                0XFFF7 /* Samples multiple channels individually in sequence */

#define ADC_AUTO_SAMPLING_ON        0xFFFF /* Sampling begins immediately after last conversion */
#define ADC_AUTO_SAMPLING_OFF       0xFFFB /* Sampling begins when SAMP bit is set */

#define ADC_SAMP_ON                 0xFFFF /* sample / hold amplifiers are sampling */
#define ADC_SAMP_OFF                0xFFFD /* sample / hold amplifiers are holding */

/* defines for the ADCON2 register */

#define ADC_VREF_AVDD_AVSS          0x0FFF /* A/D Voltage reference configuration Vref+ is AVdd and Vref- is AVss */
#define ADC_VREF_EXT_AVSS           0x2FFF /* A/D Voltage reference configuration Vref+ external and Vref- is AVss */
#define ADC_VREF_AVDD_EXT           0x4FFF /* A/D Voltage reference configuration Vref+ AVdd and Vref- external */
#define ADC_VREF_EXT_EXT            0x6FFF /* A/D Voltage reference configuration both Vref+ and Vref- are external */

#define ADC_SCAN_ON                 0xEFFF /* A/D Scan Input Selections for CH0 during SAMPLE A */
#define ADC_SCAN_OFF                0xEBFF /* A/D Do notScan Input Selections for CH0+ during SAMPLE A */

#define ADC_SELECT_CHAN_0123        0xEFFF /* Converts CH0, CH1, CH2 and CH3 */
#define ADC_SELECT_CHAN_01          0xEDFF /* Converts CH0 and CH1 */
#define ADC_SELECT_CHAN_0           0xECFF /* Converts CH0 */

#define ADC_BUF_FILL_0x8_0xF        0xEFFF /*ADC is currently filling buffer 0x8-0xF*/
#define ADC_BUF_FILL_0x0_0x7        0xEF7F /*ADC is currently filling buffer 0x0-0x7 */

#define ADC_DMA_ADD_INC_1       0xEFC3 /* DMA address increment after conversion of each sample */
#define ADC_DMA_ADD_INC_2       0xEFC7 /* DMA address increment after conversion of 2 samples */
#define ADC_DMA_ADD_INC_3       0xEFCB /* DMA address increment after conversion of 3 samples */
#define ADC_DMA_ADD_INC_4       0xEFCF /* DMA address increment after conversion of 4 samples */
#define ADC_DMA_ADD_INC_5       0xEFD3 /* DMA address increment after conversion of 5 samples */
#define ADC_DMA_ADD_INC_6       0xEFD7 /* DMA address increment after conversion of 6 samples */
#define ADC_DMA_ADD_INC_7       0xEFDB /* DMA address increment after conversion of 7 samples */
#define ADC_DMA_ADD_INC_8       0xEFDF /* DMA address increment after conversion of 8 samples */
#define ADC_DMA_ADD_INC_9       0xEFE3 /* DMA address increment after conversion of 9 samples */
#define ADC_DMA_ADD_INC_10      0xEFE7 /* DMA address increment after conversion of 10 samples */
#define ADC_DMA_ADD_INC_11      0xEFEB /* DMA address increment after conversion of 11 samples */
#define ADC_DMA_ADD_INC_12      0xEFEF /* DMA address increment after conversion of 12 samples */
#define ADC_DMA_ADD_INC_13      0xEFF3 /* DMA address increment after conversion of 13 samples */
#define ADC_DMA_ADD_INC_14      0xEFF7 /* DMA address increment after conversion of 14 samples */
#define ADC_DMA_ADD_INC_15      0xEFFB /* DMA address increment after conversion of 15 samples */
#define ADC_DMA_ADD_INC_16      0xEFFF /* DMA address increment after conversion of 16 samples */

/* BUFM bit defines */

#define ADC_ALT_BUF_ON              0xEFFF /* Buffer configured as 2 8-word buffers */
#define ADC_ALT_BUF_OFF             0xEFFD /* Buffer configured as 1 16-word buffer */

/* A/D Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next sample */
#define ADC_ALT_INPUT_ON            0xEFFF /* alternate between MUXA and MUXB */

/* A/D Always uses channel input selects for SAMPLE A */
#define ADC_ALT_INPUT_OFF           0xEFFE /* use MUXA only */

/* defines for ADCON3 register */
#define ADC_SAMPLE_TIME_0           0xE0FF /* A/D Auto Sample Time 0 Tad */
#define ADC_SAMPLE_TIME_1           0xE1FF /* A/D Auto Sample Time 1 Tad */
#define ADC_SAMPLE_TIME_2           0xE2FF /* A/D Auto Sample Time 2 Tad */
#define ADC_SAMPLE_TIME_3           0xE3FF /* A/D Auto Sample Time 3 Tad */
#define ADC_SAMPLE_TIME_4           0xE4FF /* A/D Auto Sample Time 4 Tad */
#define ADC_SAMPLE_TIME_5           0xE5FF /* A/D Auto Sample Time 5 Tad */
#define ADC_SAMPLE_TIME_6           0xE6FF /* A/D Auto Sample Time 6 Tad */
#define ADC_SAMPLE_TIME_7           0xE7FF /* A/D Auto Sample Time 7 Tad */
#define ADC_SAMPLE_TIME_8           0xE8FF /* A/D Auto Sample Time 8 Tad */
#define ADC_SAMPLE_TIME_9           0xE9FF /* A/D Auto Sample Time 9 Tad */
#define ADC_SAMPLE_TIME_10          0xEAFF /* A/D Auto Sample Time 10 Tad */
#define ADC_SAMPLE_TIME_11          0xEBFF /* A/D Auto Sample Time 11 Tad */
#define ADC_SAMPLE_TIME_12          0xECFF /* A/D Auto Sample Time 12 Tad */
#define ADC_SAMPLE_TIME_13          0xEDFF /* A/D Auto Sample Time 13 Tad */
#define ADC_SAMPLE_TIME_14          0xEEFF /* A/D Auto Sample Time 14 Tad */
#define ADC_SAMPLE_TIME_15          0xEFFF /* A/D Auto Sample Time 15 Tad */
#define ADC_SAMPLE_TIME_16          0xF0FF /* A/D Auto Sample Time 16 Tad */
#define ADC_SAMPLE_TIME_17          0xF1FF /* A/D Auto Sample Time 17 Tad */
#define ADC_SAMPLE_TIME_18          0xF2FF /* A/D Auto Sample Time 18 Tad */
#define ADC_SAMPLE_TIME_19          0xF3FF /* A/D Auto Sample Time 19 Tad */
#define ADC_SAMPLE_TIME_20          0xF4FF /* A/D Auto Sample Time 20 Tad */
#define ADC_SAMPLE_TIME_21          0xF5FF /* A/D Auto Sample Time 21 Tad */
#define ADC_SAMPLE_TIME_22          0xF6FF /* A/D Auto Sample Time 22 Tad */
#define ADC_SAMPLE_TIME_23          0xF7FF /* A/D Auto Sample Time 23 Tad */
#define ADC_SAMPLE_TIME_24          0xF8FF /* A/D Auto Sample Time 24 Tad */
#define ADC_SAMPLE_TIME_25          0xF9FF /* A/D Auto Sample Time 25 Tad */
#define ADC_SAMPLE_TIME_26          0xFAFF /* A/D Auto Sample Time 26 Tad */
#define ADC_SAMPLE_TIME_27          0xFBFF /* A/D Auto Sample Time 27 Tad */
#define ADC_SAMPLE_TIME_28          0xFCFF /* A/D Auto Sample Time 28 Tad */
#define ADC_SAMPLE_TIME_29          0xFDFF /* A/D Auto Sample Time 29 Tad */
#define ADC_SAMPLE_TIME_30          0xFEFF /* A/D Auto Sample Time 30 Tad */
#define ADC_SAMPLE_TIME_31          0xFFFF /* A/D Auto Sample Time 31 Tad */

/* A/D Conversion Clock Source internal RC Clock */
#define ADC_CONV_CLK_INTERNAL_RC    0xFFFF
/* A/D Conversion Clock Source Clock derived from system clock */
#define ADC_CONV_CLK_SYSTEM         0x7FFF

/* A/D conversion clock select bit ADCS<5:0>*/
#define ADC_CONV_CLK_32Tcy          0xFFFF  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_63Tcy2         0xFFFE  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_31Tcy          0xFFFD  /* A/D Conversion Clock Select bits */
#define ADC_CONV_CLK_61Tcy2         0xFFFC  /* A/D Conversion Clock Select bits */