dma.h

Mplab C30编译器

#define DMA6_PERIPHERAL_INDIRECT     0xFF2F /* Peripheral indirect addressing mode*/
#define DMA6_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA6_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA6_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA6_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA6_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA6_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

/* DMA7CON Configuration Bit Definitions */

#define DMA7_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA7_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA7_SIZE_BYTE               0xFFFF /* DMA7 data size is byte */
#define DMA7_SIZE_WORD               0xBFFF /* DMA7 data size is word */

#define DMA7_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA7           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA7_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA7_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA7_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA7_NORMAL                  0xF7FF /* Normal operation*/

#define DMA7_PERIPHERAL_INDIRECT     0xFF2F /* Peripheral indirect addressing mode*/
#define DMA7_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA7_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA7_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA7_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA7_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA7_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

 /*DMA0REQ bit definitions*/

#define DMA0_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA0_AUTOMATIC               0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /*DMA1REQ bit definitions*/

#define DMA1_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA1_AUTOMATIC               0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /*DMA2REQ bit definitions*/

#define DMA2_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA2_AUTOMATIC               0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /*DMA3REQ bit definitions*/

#define DMA3_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA3_AUTOMATIC               0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /*DMA4REQ bit definitions*/

#define DMA4_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA4_AUTOMATIC               0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /*DMA5REQ bit definitions*/

#define DMA5_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA5_AUTOMATIC               0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /*DMA6REQ bit definitions*/

#define DMA6_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA6_AUTOMATIC               0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /*DMA7REQ bit definitions*/

#define DMA7_MANUAL                  0xFFFF /* Force a single DMA transfer (Manual Mode)*/
#define DMA7_AUTOMATIC            0x7FFF /* Automatic DMA transfer initiation by DMA request*/

 /* DMA controller status register 0 */

#define CHAN7_PERI_WRITE_COLLISION    0xFFFF /*channel 7 peripheral write collision detected*/
#define CHAN7_PERI_NO_WRITE_COLLISION    0x7FFF /*channel 7 peripheral write collision not detected*/
#define CHAN6_PERI_WRITE_COLLISION    0xFFFF /*channel 6 peripheral write collision detected*/
#define CHAN6_PERI_NO_WRITE_COLLISION    0xBFFF /*channel 6 peripheral write collision not detected*/
#define CHAN5_PERI_WRITE_COLLISION    0xFFFF /*channel 5 peripheral write collision detected*/
#define CHAN5_PERI_NO_WRITE_COLLISION    0xDFFF /*channel 5 peripheral write collision not detected*/
#define CHAN4_PERI_WRITE_COLLISION    0xFFFF /*channel 4 peripheral write collision detected*/
#define CHAN4_PERI_NO_WRITE_COLLISION    0xEFFF /*channel 4 peripheral write collision not detected*/
#define CHAN3_PERI_WRITE_COLLISION    0xFFFF /*channel 3 peripheral write collision detected*/
#define CHAN3_PERI_NO_WRITE_COLLISION    0xF7FF /*channel 3 peripheral write collision not detected*/
#define CHAN2_PERI_WRITE_COLLISION    0xFFFF /*channel 2 peripheral write collision detected*/
#define CHAN2_PERI_NO_WRITE_COLLISION    0xFBFF /*channel 2 peripheral write collision not detected*/
#define CHAN1_PERI_WRITE_COLLISION    0xFFFF /*channel 1 peripheral write collision detected*/
#define CHAN1_PERI_NO_WRITE_COLLISION    0xFDFF /*channel 1 peripheral write collision not detected*/
#define CHAN0_PERI_WRITE_COLLISION    0xFFFF /*channel 0 peripheral write collision detected*/
#define CHAN0_PERI_NO_WRITE_COLLISION    0xFEFF /*channel 0 peripheral write collision not detected*/

#define CHAN7_DMARAM_WRITE_COLLISION    0xFFFF /*channel 7 DMA RAM write collision detected*/
#define CHAN7_DMARAM_NO_WRITE_COLLISION    0xFF7F /*channel 7 DMA RAM write collision detected*/
#define CHAN6_DMARAM_WRITE_COLLISION    0xFFFF /*channel 6 DMA RAM write collision detected*/
#define CHAN6_DMARAM_NO_WRITE_COLLISION    0xFFBF /*channel 6 DMA RAM write collision detected*/
#define CHAN5_DMARAM_WRITE_COLLISION    0xFFFF /*channel 5 DMA RAM write collision detected*/
#define CHAN5_DMARAM_NO_WRITE_COLLISION    0xFFDF /*channel 5 DMA RAM write collision detected*/
#define CHAN4_DMARAM_WRITE_COLLISION    0xFFFF /*channel 4 DMA RAM write collision detected*/
#define CHAN4_DMARAM_NO_WRITE_COLLISION    0xFFEF /*channel 4 DMA RAM write collision detected*/
#define CHAN3_DMARAM_WRITE_COLLISION    0xFFFF /*channel 3 DMA RAM write collision detected*/
#define CHAN3_DMARAM_NO_WRITE_COLLISION    0xFFF7 /*channel 3 DMA RAM write collision detected*/
#define CHAN2_DMARAM_WRITE_COLLISION    0xFFFF /*channel 2 DMA RAM write collision detected*/
#define CHAN2_DMARAM_NO_WRITE_COLLISION    0xFFFB /*channel 2 DMA RAM write collision detected*/
#define CHAN1_DMARAM_WRITE_COLLISION    0xFFFF /*channel 1 DMA RAM write collision detected*/
#define CHAN1_DMARAM_NO_WRITE_COLLISION    0xFFFD /*channel 1 DMA RAM write collision detected*/
#define CHAN0_DMARAM_WRITE_COLLISION    0xFFFF /*channel 0 DMA RAM write collision detected*/
#define CHAN0_DMARAM_NO_WRITE_COLLISION    0xFFFE /*channel 0 DMA RAM write collision detected*/

 /*DMA controller status register 1 */

#define LAST_DMA_ACTIVE_CHANNEL7    0xF7FF /* Last data transfer was by DMA channel 7*/
#define LAST_DMA_ACTIVE_CHANNEL6    0xF6FF /* Last data transfer was by DMA channel 6*/
#define LAST_DMA_ACTIVE_CHANNEL5    0xF5FF /* Last data transfer was by DMA channel 5*/
#define LAST_DMA_ACTIVE_CHANNEL4    0xF4FF /* Last data transfer was by DMA channel 4*/
#define LAST_DMA_ACTIVE_CHANNEL3    0xF3FF /* Last data transfer was by DMA channel 3*/
#define LAST_DMA_ACTIVE_CHANNEL2    0xF2FF /* Last data transfer was by DMA channel 2*/
#define LAST_DMA_ACTIVE_CHANNEL1    0xF1FF /* Last data transfer was by DMA channel 1*/
#define LAST_DMA_ACTIVE_CHANNEL0    0xF0FF /* Last data transfer was by DMA channel 0*/

#define PING_PONG_DMA7STB           0xFFFF /*Channel 7 STB register selected for Ping-Pong*/
#define PING_PONG_DMA7STA           0xFF7F /*Channel 7 STA register selected for Ping-Pong*/
#define PING_PONG_DMA6STB           0xFFFF /*Channel 6 STB register selected for Ping-Pong*/
#define PING_PONG_DMA6STA           0xFFBF /*Channel 7 STA register selected for Ping-Pong*/
#define PING_PONG_DMA5STB           0xFFFF /*Channel 5 STB register selected for Ping-Pong*/
#define PING_PONG_DMA5STA           0xFFDF /*Channel 7 STA register selected for Ping-Pong*/
#define PING_PONG_DMA4STB           0xFFFF /*Channel 4 STB register selected for Ping-Pong*/
#define PING_PONG_DMA4STA           0xFFEF /*Channel 7 STA register selected for Ping-Pong*/
#define PING_PONG_DMA3STB           0xFFFF /*Channel 3 STB register selected for Ping-Pong*/
#define PING_PONG_DMA3STA           0xFFF7 /*Channel 7 STA register selected for Ping-Pong*/
#define PING_PONG_DMA2STB           0xFFFF /*Channel 2 STB register selected for Ping-Pong*/
#define PING_PONG_DMA2STA           0xFFFB /*Channel 7 STA register selected for Ping-Pong*/
#define PING_PONG_DMA1STB           0xFFFF /*Channel 1 STB register selected for Ping-Pong*/
#define PING_PONG_DMA1STA           0xFFFD /*Channel 7 STA register selected for Ping-Pong*/
#define PING_PONG_DMA0STB           0xFFFF /*Channel 0 STB register selected for Ping-Pong*/
#define PING_PONG_DMA0STA           0xFFFE /*Channel 7 STA register selected for Ping-Pong*/

/* Setting the priority of DMA0 interrupt */
#define DMA0_INT_PRI_0                   0xFFF8
#define DMA0_INT_PRI_1                   0xFFF9
#define DMA0_INT_PRI_2                   0xFFFA
#define DMA0_INT_PRI_3                   0xFFFB
#define DMA0_INT_PRI_4                   0xFFFC
#define DMA0_INT_PRI_5                   0xFFFD
#define DMA0_INT_PRI_6                   0xFFFE
#define DMA0_INT_PRI_7                   0xFFFF

/* Setting the priority of DMA1 interrupt */
#define DMA1_INT_PRI_0                   0xFFF8
#define DMA1_INT_PRI_1                   0xFFF9
#define DMA1_INT_PRI_2                   0xFFFA
#define DMA1_INT_PRI_3                   0xFFFB
#define DMA1_INT_PRI_4                   0xFFFC
#define DMA1_INT_PRI_5                   0xFFFD
#define DMA1_INT_PRI_6                   0xFFFE
#define DMA1_INT_PRI_7                   0xFFFF

/* Setting the priority of DMA2 interrupt */
#define DMA2_INT_PRI_0                   0xFFF8
#define DMA2_INT_PRI_1                   0xFFF9
#define DMA2_INT_PRI_2                   0xFFFA
#define DMA2_INT_PRI_3                   0xFFFB
#define DMA2_INT_PRI_4                   0xFFFC
#define DMA2_INT_PRI_5                   0xFFFD
#define DMA2_INT_PRI_6                   0xFFFE
#define DMA2_INT_PRI_7                   0xFFFF

/* Setting the priority of DMA3 interrupt */
#define DMA3_INT_PRI_0                   0xFFF8
#define DMA3_INT_PRI_1                   0xFFF9
#define DMA3_INT_PRI_2                   0xFFFA
#define DMA3_INT_PRI_3                   0xFFFB
#define DMA3_INT_PRI_4                   0xFFFC
#define DMA3_INT_PRI_5                   0xFFFD
#define DMA3_INT_PRI_6                   0xFFFE
#define DMA3_INT_PRI_7                   0xFFFF

/* Setting the priority of DMA4 interrupt */
#define DMA4_INT_PRI_0                   0xFFF8
#define DMA4_INT_PRI_1                   0xFFF9
#define DMA4_INT_PRI_2                   0xFFFA
#define DMA4_INT_PRI_3                   0xFFFB
#define DMA4_INT_PRI_4                   0xFFFC
#define DMA4_INT_PRI_5                   0xFFFD
#define DMA4_INT_PRI_6                   0xFFFE
#define DMA4_INT_PRI_7                   0xFFFF

/* Setting the priority of DMA5 interrupt */
#define DMA5_INT_PRI_0                   0xFFF8
#define DMA5_INT_PRI_1                   0xFFF9
#define DMA5_INT_PRI_2                   0xFFFA
#define DMA5_INT_PRI_3                   0xFFFB
#define DMA5_INT_PRI_4                   0xFFFC
#define DMA5_INT_PRI_5                   0xFFFD
#define DMA5_INT_PRI_6                   0xFFFE
#define DMA5_INT_PRI_7                   0xFFFF

/* Setting the priority of DMA6 interrupt */
#define DMA6_INT_PRI_0                   0xFFF8
#define DMA6_INT_PRI_1                   0xFFF9
#define DMA6_INT_PRI_2                   0xFFFA
#define DMA6_INT_PRI_3                   0xFFFB
#define DMA6_INT_PRI_4                   0xFFFC
#define DMA6_INT_PRI_5                   0xFFFD
#define DMA6_INT_PRI_6                   0xFFFE
#define DMA6_INT_PRI_7                   0xFFFF

/* Setting the priority of DMA7 interrupt */
#define DMA7_INT_PRI_0                   0xFFF8
#define DMA7_INT_PRI_1                   0xFFF9
#define DMA7_INT_PRI_2                   0xFFFA
#define DMA7_INT_PRI_3                   0xFFFB
#define DMA7_INT_PRI_4                   0xFFFC
#define DMA7_INT_PRI_5                   0xFFFD
#define DMA7_INT_PRI_6                   0xFFFE