dma.h

Mplab C30编译器

/********************************************************************/
/*              Header for DMA module library functions             */
/********************************************************************/

#if defined(__dsPIC33F__)
#include <p33Fxxxx.h>
#elif defined(__PIC24H__)
#include <p24Hxxxx.h>
#else
#error "Does not build on this target"
#endif

#ifndef __DMA_H
#define __DMA_H

/* List of SFRs for DMA */
/* This list contains the SFRs with default (POR) values to be used for configuring DMA */
/* The user can modify this based on the requirement */

#define DMA0CON_VALUE                0x0000
#define DMA1CON_VALUE                0x0000
#define DMA2CON_VALUE                0x0000
#define DMA3CON_VALUE                0x0000
#define DMA4CON_VALUE                0x0000
#define DMA5CON_VALUE                0x0000
#define DMA6CON_VALUE                0x0000
#define DMA7CON_VALUE                0x0000

/* DMA0CON Configuration Bit Definitions */

#define DMA0_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA0_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA0_SIZE_BYTE               0xFFFF /* DMA0 data size is byte */
#define DMA0_SIZE_WORD               0xBFFF /* DMA0 data size is word */

#define DMA0_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA0           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA0_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA0_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA0_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA0_NORMAL                  0xF7FF /* Normal operation*/

#define DMA0_PERIPHERAL_INDIRECT     0xFF2F /* Peripheral indirect addressing mode*/
#define DMA0_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA0_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA0_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA0_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA0_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA0_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

/* DMA1CON Configuration Bit Definitions */

#define DMA1_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA1_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA1_SIZE_BYTE               0xFFFF /* DMA1 data size is byte */
#define DMA1_SIZE_WORD               0xBFFF /* DMA1 data size is word */

#define DMA1_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA1           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA1_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA1_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA1_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA1_NORMAL                  0xF7FF /* Normal operation*/

#define DMA1_PERIPHERAL_INDIRECT     0xFF2F /* Peripheral indirect addressing mode*/
#define DMA1_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA1_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA1_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA1_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA1_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA1_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

/* DMA2CON Configuration Bit Definitions */

#define DMA2_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA2_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA2_SIZE_BYTE               0xFFFF /* DMA2 data size is byte */
#define DMA2_SIZE_WORD               0xBFFF /* DMA2 data size is word */

#define DMA2_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA2           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA2_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA2_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA2_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA2_NORMAL                  0xF7FF /* Normal operation*/

#define DMA2_PERIPHERAL_INDIRECT     0xFF2F /* Peripheral indirect addressing mode*/
#define DMA2_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA2_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA2_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA2_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA2_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA2_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

/* DMA3CON Configuration Bit Definitions */

#define DMA3_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA3_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA3_SIZE_BYTE               0xFFFF /* DMA3 data size is byte */
#define DMA3_SIZE_WORD               0xBFFF /* DMA3 data size is word */

#define DMA3_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA3           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA3_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA3_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA3_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA3_NORMAL                  0xF7FF /* Normal operation*/

#define DMA3_PERIPHERAL_INDIRECT     0xFF2F /* Peripheral indirect addressing mode*/
#define DMA3_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA3_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA3_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA3_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA3_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA3_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

/* DMA4CON Configuration Bit Definitions */

#define DMA4_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA4_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA4_SIZE_BYTE               0xFFFF /* DMA4 data size is byte */
#define DMA4_SIZE_WORD               0xBFFF /* DMA4 data size is word */

#define DMA4_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA4           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA4_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA4_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA4_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA4_NORMAL                  0xF7FF /* Normal operation*/

#define DMA4_PERIPHERAL_INDIRECT     0xFF2F /* Peripheral indirect addressing mode*/
#define DMA4_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA4_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA4_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA4_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA4_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA4_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

/* DMA5CON Configuration Bit Definitions */

#define DMA5_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA5_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA5_SIZE_BYTE               0xFFFF /* DMA5 data size is byte */
#define DMA5_SIZE_WORD               0xBFFF /* DMA5 data size is word */

#define DMA5_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA5           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA5_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA5_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA5_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA5_NORMAL                  0xF7FF /* Normal operation*/

#define DMA5_PERIPHERAL_INDIREC T    0xFF2F /* Peripheral indirect addressing mode*/
#define DMA5_REGISTER                0xFF1F /* Register indirect without post increment*/
#define DMA5_REGISTER_POST_INCREMENT  0xFF0F /* Register indirect with post-incrmenent mode*/

#define DMA5_ONE_SHOT_PING_PONG      0xFFFF /* One-Shot, Ping-Pong modes enabled*/
#define DMA5_CONTINUOUS_PING_PONG    0xFFF2 /* Continuous Ping-Pong modes enabled*/
#define DMA5_ONE_SHOT                0xFFF1 /* One-shot Ping-Pong mode disabled*/
#define DMA5_CONTINUOUS              0xFFF0 /* Continuous Ping-Pong modes disabled */

/* DMA6CON Configuration Bit Definitions */

#define DMA6_MODULE_ON               0xFFFF /* A/D Converter on */
#define DMA6_MODULE_OFF              0x7FFF /* A/D Converter off */

#define DMA6_SIZE_BYTE               0xFFFF /* DMA6 data size is byte */
#define DMA6_SIZE_WORD               0xBFFF /* DMA6 data size is word */

#define DMA6_TO_PERIPHERAL           0xFFFF /* Read from DMA RAM address, write to peripheral*/
#define PERIPHERAL_TO_DMA6           0xDFFF /* Read from peripheral address, write to DMA RAM*/

#define DMA6_INTERRUPT_HALF          0xFFFF /* Initiate block transfer complete interrupt
                                               when half of the data has been moved */

#define DMA6_INTERRUPT_BLOCK         0xEFFF /* Initiate block transfer complete interrupt
                                               when all of the data has been moved */

#define DMA6_WRITE_NULL              0xFFFF /* Null data write to peripheral in addition to DMA RAM write*/
#define DMA6_NORMAL                  0xF7FF /* Normal operation*/