simple.tan.qmsg

来自「使用verilog语言控制CPLD通过红外收发器进行红外通讯」· QMSG 代码 · 共 12 行 · 第 1/2 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ir38k:inst\|scan " "Info: Detected ripple clock \"ir38k:inst\|scan\" as buffer" {  } { { "ir38k.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/simple/ir38k.vhd" 12 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ir38k:inst\|scan" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ir38k:inst\|\\div:divfre\[1\] register ir38k:inst\|\\div:divfre\[5\] 158.93 MHz 6.292 ns Internal " "Info: Clock \"clk\" has Internal fmax of 158.93 MHz between source register \"ir38k:inst\|\\div:divfre\[1\]\" and destination register \"ir38k:inst\|\\div:divfre\[5\]\" (period= 6.292 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.583 ns + Longest register register " "Info: + Longest register to register delay is 5.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ir38k:inst\|\\div:divfre\[1\] 1 REG LC_X15_Y9_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y9_N4; Fanout = 4; REG Node = 'ir38k:inst\|\\div:divfre\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ir38k:inst|\div:divfre[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(0.747 ns) 2.042 ns ir38k:inst\|Add0~130 2 COMB LC_X14_Y9_N1 2 " "Info: 2: + IC(1.295 ns) + CELL(0.747 ns) = 2.042 ns; Loc. = LC_X14_Y9_N1; Fanout = 2; COMB Node = 'ir38k:inst\|Add0~130'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.042 ns" { ir38k:inst|\div:divfre[1] ir38k:inst|Add0~130 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.165 ns ir38k:inst\|Add0~128 3 COMB LC_X14_Y9_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.165 ns; Loc. = LC_X14_Y9_N2; Fanout = 2; COMB Node = 'ir38k:inst\|Add0~128'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { ir38k:inst|Add0~130 ir38k:inst|Add0~128 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.288 ns ir38k:inst\|Add0~126 4 COMB LC_X14_Y9_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.288 ns; Loc. = LC_X14_Y9_N3; Fanout = 2; COMB Node = 'ir38k:inst\|Add0~126'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { ir38k:inst|Add0~128 ir38k:inst|Add0~126 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 2.549 ns ir38k:inst\|Add0~122 5 COMB LC_X14_Y9_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.261 ns) = 2.549 ns; Loc. = LC_X14_Y9_N4; Fanout = 3; COMB Node = 'ir38k:inst\|Add0~122'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { ir38k:inst|Add0~126 ir38k:inst|Add0~122 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 3.524 ns ir38k:inst\|Add0~123 6 COMB LC_X14_Y9_N5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.975 ns) = 3.524 ns; Loc. = LC_X14_Y9_N5; Fanout = 1; COMB Node = 'ir38k:inst\|Add0~123'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { ir38k:inst|Add0~122 ir38k:inst|Add0~123 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.779 ns) + CELL(0.280 ns) 5.583 ns ir38k:inst\|\\div:divfre\[5\] 7 REG LC_X15_Y9_N6 4 " "Info: 7: + IC(1.779 ns) + CELL(0.280 ns) = 5.583 ns; Loc. = LC_X15_Y9_N6; Fanout = 4; REG Node = 'ir38k:inst\|\\div:divfre\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.059 ns" { ir38k:inst|Add0~123 ir38k:inst|\div:divfre[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.509 ns ( 44.94 % ) " "Info: Total cell delay = 2.509 ns ( 44.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.074 ns ( 55.06 % ) " "Info: Total interconnect delay = 3.074 ns ( 55.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.583 ns" { ir38k:inst|\div:divfre[1] ir38k:inst|Add0~130 ir38k:inst|Add0~128 ir38k:inst|Add0~126 ir38k:inst|Add0~122 ir38k:inst|Add0~123 ir38k:inst|\div:divfre[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.583 ns" { ir38k:inst|\div:divfre[1] {} ir38k:inst|Add0~130 {} ir38k:inst|Add0~128 {} ir38k:inst|Add0~126 {} ir38k:inst|Add0~122 {} ir38k:inst|Add0~123 {} ir38k:inst|\div:divfre[5] {} } { 0.000ns 1.295ns 0.000ns 0.000ns 0.000ns 0.000ns 1.779ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.261ns 0.975ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 9 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "simple.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/simple/simple.bdf" { { 88 88 256 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns ir38k:inst\|\\div:divfre\[5\] 2 REG LC_X15_Y9_N6 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X15_Y9_N6; Fanout = 4; REG Node = 'ir38k:inst\|\\div:divfre\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk ir38k:inst|\div:divfre[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk ir38k:inst|\div:divfre[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} ir38k:inst|\div:divfre[5] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 9 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "simple.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/simple/simple.bdf" { { 88 88 256 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns ir38k:inst\|\\div:divfre\[1\] 2 REG LC_X15_Y9_N4 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X15_Y9_N4; Fanout = 4; REG Node = 'ir38k:inst\|\\div:divfre\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk ir38k:inst|\div:divfre[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk ir38k:inst|\div:divfre[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} ir38k:inst|\div:divfre[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk ir38k:inst|\div:divfre[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} ir38k:inst|\div:divfre[5] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk ir38k:inst|\div:divfre[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} ir38k:inst|\div:divfre[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.583 ns" { ir38k:inst|\div:divfre[1] ir38k:inst|Add0~130 ir38k:inst|Add0~128 ir38k:inst|Add0~126 ir38k:inst|Add0~122 ir38k:inst|Add0~123 ir38k:inst|\div:divfre[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.583 ns" { ir38k:inst|\div:divfre[1] {} ir38k:inst|Add0~130 {} ir38k:inst|Add0~128 {} ir38k:inst|Add0~126 {} ir38k:inst|Add0~122 {} ir38k:inst|Add0~123 {} ir38k:inst|\div:divfre[5] {} } { 0.000ns 1.295ns 0.000ns 0.000ns 0.000ns 0.000ns 1.779ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.261ns 0.975ns 0.280ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk ir38k:inst|\div:divfre[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} ir38k:inst|\div:divfre[5] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk ir38k:inst|\div:divfre[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} ir38k:inst|\div:divfre[1] {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk c_wave ir38k:inst\|\\i38k:t0\[0\] 17.642 ns register " "Info: tco from clock \"clk\" to destination pin \"c_wave\" through register \"ir38k:inst\|\\i38k:t0\[0\]\" is 17.642 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.250 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.250 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 9 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "simple.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/simple/simple.bdf" { { 88 88 256 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns ir38k:inst\|scan 2 REG LC_X15_Y9_N7 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y9_N7; Fanout = 3; REG Node = 'ir38k:inst\|scan'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk ir38k:inst|scan } "NODE_NAME" } } { "ir38k.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/simple/ir38k.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.137 ns) + CELL(0.918 ns) 10.250 ns ir38k:inst\|\\i38k:t0\[0\] 3 REG LC_X10_Y6_N2 3 " "Info: 3: + IC(5.137 ns) + CELL(0.918 ns) = 10.250 ns; Loc. = LC_X10_Y6_N2; Fanout = 3; REG Node = 'ir38k:inst\|\\i38k:t0\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.055 ns" { ir38k:inst|scan ir38k:inst|\i38k:t0[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 32.93 % ) " "Info: Total cell delay = 3.375 ns ( 32.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.875 ns ( 67.07 % ) " "Info: Total interconnect delay = 6.875 ns ( 67.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.250 ns" { clk ir38k:inst|scan ir38k:inst|\i38k:t0[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.250 ns" { clk {} clk~combout {} ir38k:inst|scan {} ir38k:inst|\i38k:t0[0] {} } { 0.000ns 0.000ns 1.738ns 5.137ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.016 ns + Longest register pin " "Info: + Longest register to pin delay is 7.016 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ir38k:inst\|\\i38k:t0\[0\] 1 REG LC_X10_Y6_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N2; Fanout = 3; REG Node = 'ir38k:inst\|\\i38k:t0\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ir38k:inst|\i38k:t0[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.740 ns) 1.675 ns ir38k:inst\|c_wave 2 COMB LC_X10_Y6_N8 1 " "Info: 2: + IC(0.935 ns) + CELL(0.740 ns) = 1.675 ns; Loc. = LC_X10_Y6_N8; Fanout = 1; COMB Node = 'ir38k:inst\|c_wave'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.675 ns" { ir38k:inst|\i38k:t0[0] ir38k:inst|c_wave } "NODE_NAME" } } { "ir38k.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/simple/ir38k.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.019 ns) + CELL(2.322 ns) 7.016 ns c_wave 3 PIN PIN_107 0 " "Info: 3: + IC(3.019 ns) + CELL(2.322 ns) = 7.016 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'c_wave'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.341 ns" { ir38k:inst|c_wave c_wave } "NODE_NAME" } } { "simple.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/simple/simple.bdf" { { 72 520 696 88 "c_wave" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.062 ns ( 43.64 % ) " "Info: Total cell delay = 3.062 ns ( 43.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.954 ns ( 56.36 % ) " "Info: Total interconnect delay = 3.954 ns ( 56.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.016 ns" { ir38k:inst|\i38k:t0[0] ir38k:inst|c_wave c_wave } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.016 ns" { ir38k:inst|\i38k:t0[0] {} ir38k:inst|c_wave {} c_wave {} } { 0.000ns 0.935ns 3.019ns } { 0.000ns 0.740ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.250 ns" { clk ir38k:inst|scan ir38k:inst|\i38k:t0[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.250 ns" { clk {} clk~combout {} ir38k:inst|scan {} ir38k:inst|\i38k:t0[0] {} } { 0.000ns 0.000ns 1.738ns 5.137ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.016 ns" { ir38k:inst|\i38k:t0[0] ir38k:inst|c_wave c_wave } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.016 ns" { ir38k:inst|\i38k:t0[0] {} ir38k:inst|c_wave {} c_wave {} } { 0.000ns 0.935ns 3.019ns } { 0.000ns 0.740ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "din c_wave 9.693 ns Longest " "Info: Longest tpd from source pin \"din\" to destination pin \"c_wave\" is 9.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns din 1 PIN PIN_51 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 'din'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { din } "NODE_NAME" } } { "simple.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/simple/simple.bdf" { { 104 88 256 120 "din" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.709 ns) + CELL(0.511 ns) 4.352 ns ir38k:inst\|c_wave 2 COMB LC_X10_Y6_N8 1 " "Info: 2: + IC(2.709 ns) + CELL(0.511 ns) = 4.352 ns; Loc. = LC_X10_Y6_N8; Fanout = 1; COMB Node = 'ir38k:inst\|c_wave'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.220 ns" { din ir38k:inst|c_wave } "NODE_NAME" } } { "ir38k.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/simple/ir38k.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.019 ns) + CELL(2.322 ns) 9.693 ns c_wave 3 PIN PIN_107 0 " "Info: 3: + IC(3.019 ns) + CELL(2.322 ns) = 9.693 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'c_wave'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.341 ns" { ir38k:inst|c_wave c_wave } "NODE_NAME" } } { "simple.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/simple/simple.bdf" { { 72 520 696 88 "c_wave" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.965 ns ( 40.91 % ) " "Info: Total cell delay = 3.965 ns ( 40.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.728 ns ( 59.09 % ) " "Info: Total interconnect delay = 5.728 ns ( 59.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.693 ns" { din ir38k:inst|c_wave c_wave } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.693 ns" { din {} din~combout {} ir38k:inst|c_wave {} c_wave {} } { 0.000ns 0.000ns 2.709ns 3.019ns } { 0.000ns 1.132ns 0.511ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 01 16:12:05 2008 " "Info: Processing ended: Mon Sep 01 16:12:05 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}