recive.map.summary

使用verilog语言控制CPLD通过红外收发器进行红外通讯

Analysis & Synthesis Status : Successful - Mon Sep 01 20:56:29 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : recive
Top-level Entity Name : recive
Family : MAX II
Total logic elements : 0
Total pins : 4
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0