sysalib.s

BSP for S3C2410

/* sysALib.s - Samsung SBC ARM9 system-dependent routines */

/* Copyright 1984-2001 Wind River Systems, Inc. */



#define _ASMLANGUAGE
#include "vxWorks.h"
#include "arch/arm/arm.h"
#include "regs.h"
#include "sysLib.h"
#include "config.h"
#include "wrSbcArm9.h"

    .data
    .globl  FUNC(copyright_wind_river)
    .long   FUNC(copyright_wind_river)

    .globl    FUNC(sysInit)        
    .globl    FUNC(sysIntStackSplit)   


    .extern    FUNC(usrInit)       

    .extern    FUNC(vxSvcIntStackBase)   
    .extern    FUNC(vxSvcIntStackEnd)   
    .extern    FUNC(vxIrqIntStackBase)    
    .extern    FUNC(vxIrqIntStackEnd)    

    .text
    .balign 4

/*******************************************************************************
*
* sysInit - start after boot
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A

* sysInit ()              /@ THIS IS NOT A CALLABLE ROUTINE @/

*/

_ARM_FUNCTION(sysInit)

#ifdef  INCLUDE_VWARE_LAUNCH
    LDR    r2, =sysPrivateVwareParams
    STR    r1, [r2]
    LDR    r2, =sysPrivateVwareParams + 0x04
    STR    r0, [r2]
#endif /* INCLUDE_VWARE_LAUNCH */

    LDR    r2, L$_SbcArm9Intmsk		
    MOV    r1, #0x07ffffff
    STR    r1, [r2]

#if 0
    /* disable interrupts and force SVC32 mode, just like reset */

    MRS    r1, cpsr
    BIC    r1, r1, #MASK_MODE
    ORR    r1, r1, #MODE_SVC32 | I_BIT | F_BIT
    MSR    cpsr, r1

    /*
     * CPU INTERRUPTS DISABLED
     *
     * disable individual interrupts in the interrupt controller
     */
    LDR    r2, L$_SbcArm9Intmsk            /* R2->interrupt controller */
    MVN    r1, #0                /* &FFFFFFFF */
    STR    r1, [r2]            /* disable all interrupt soucres */
#endif


    LDR    sp, L$_STACK_ADDR
    MOV    fp, #0            


    MOV    fp, #0            /* initialize frame pointer */
    MOV    r0, #BOOT_WARM_AUTOBOOT    /* pass startType */

#if    (CPU == ARMARCH4_T)
    LDR    r12, L$_usrInit
    BX     r12
#else
    B     FUNC(usrInit)
#endif    /* (CPU == ARMARCH4_T) */


/*******************************************************************************
*
* sysIntStackSplit - split interrupt stack and set interrupt stack pointers
*
*/


_ARM_FUNCTION_CALLED_FROM_C(sysIntStackSplit)


    SUB    r2, r0, r1           
    LDR    r3, L$_vxSvcIntStackEnd
    STR    r2, [r3]            /*  == end of SVC-mode stack */
    SUB    r2, r0, r1, ASR #3        /* leave 1/8 for IRQ */
    LDR    r3, L$_vxSvcIntStackBase
    STR    r2, [r3]

    /* now allocate IRQ stack, setting irq_sp */

    LDR    r3, L$_vxIrqIntStackEnd
    STR    r2, [r3]
    LDR    r3, L$_vxIrqIntStackBase
    STR    r0, [r3]

    MRS    r2, cpsr
    BIC    r3, r2, #MASK_MODE
    ORR    r3, r3, #MODE_IRQ32 | I_BIT    /* set irq_sp */
    MSR    cpsr, r3
    MOV    sp, r0

    /* switch back to original mode and return */

    MSR    cpsr, r2

#if    (CPU == ARMARCH4_T)
    BX     lr
#else
    MOV    pc, lr
#endif    /* (CPU == ARMARCH4_T) */

#ifdef INCLUDE_VWARE_LAUNCH
#include "sysAVware.s"
#endif /* INCLUDE_VWARE_LAUNCH */

/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor preforming substitution
 */

    .balign    4

L$_vxSvcIntStackBase:
    .long    FUNC(vxSvcIntStackBase)

L$_vxSvcIntStackEnd:
    .long    FUNC(vxSvcIntStackEnd)

L$_vxIrqIntStackBase:
    .long    FUNC(vxIrqIntStackBase)

L$_vxIrqIntStackEnd:
    .long    FUNC(vxIrqIntStackEnd)

#if    (CPU == ARMARCH4_T)
L$_usrInit:
    .long    FUNC(usrInit)
#endif    /* (CPU == ARMARCH4_T) */

L$_STACK_ADDR:
    .long    FUNC(sysInit)

L$_SbcArm9Intmsk:
    .long    S3C2410X_INTMASK