testbench.vhd

Xilinx_usb_jtag 下载器原理图及程序

-- VHDL Test Bench Created from source file jtag_controller.vhd -- 15:24:02 06/16/2003
--
--   Copyright (C) 2003 by J. Kearney, Bolton, Massachusetts
--
--   This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
--   This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for more details.
--
--   You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	constant NUM_TAPS : integer := 2;

	COMPONENT jtag_controller
	port
		(clk : in std_logic;
		 usb_d : inout std_logic_vector(7 downto 0);
--		 usb_rd_n : buffer std_logic;		--!!!!
		 usb_rd_n : out std_logic;		--!!!!
--		 usb_wr : buffer std_logic;	--!!!
		 usb_wr : out std_logic;	--!!!
		 usb_txe_n : in std_logic;
		 usb_rxf_n : in std_logic;
--		 usb_si : buffer std_logic;		--!!!
		 usb_si : out std_logic;		--!!!
		 jtag_tck_A : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_tck_B : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_tck_fb : in std_logic_vector(0 to NUM_TAPS-1);
		 jtag_tdo : in std_logic_vector(0 to NUM_TAPS-1);
		 jtag_tdo_term : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_tdi : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_tms : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_trst_n : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_rst_n : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_dint : out std_logic_vector(0 to NUM_TAPS-1);
		 jtag_vgnd : out std_logic_vector(0 to 3);
		 LEDs : out std_logic_vector(3 downto 0);
		 jtag_extra : inout std_logic_vector(0 to 7);
--		 debug1: out integer range 0 to 31;
		 debug1 : out std_logic_vector(4 downto 0);
		 reconfigure : out std_logic);
	END COMPONENT;

	procedure usb_out
		(byt: in std_logic_vector(7 downto 0);
		 signal usb_d : inout std_logic_vector(7 downto 0);
		 signal usb_rd_n : in std_logic;
		 signal usb_rxf_n : out std_logic) is
	begin
		assert usb_rd_n = '1';
		usb_rxf_n <= '0';
		wait until usb_rd_n = '0';
		wait for 30 ns;
		usb_d <= byt;
		wait for 20 ns;
		assert usb_rd_n = '0';
		wait until usb_rd_n = '1';
		wait for 10 ns;
		usb_d <= (others => 'Z');
		wait for 15 ns;
		usb_rxf_n <= '1';
		wait for 80 ns;
	end procedure;

	procedure usb_in
		(signal usb_d : inout std_logic_vector(7 downto 0);
		 signal usb_wr : in std_logic;
		 signal usb_txe_n : out std_logic;
		 variable value : out std_logic_vector(7 downto 0)) is
	begin
		if usb_wr /= '1' then
			wait until usb_wr = '1';
		end if;
		wait until usb_wr = '0';
		value := usb_d;
		wait for 25 ns;
		usb_txe_n <= '1';
		wait for 80 ns;
		usb_txe_n <= '0';
	end procedure;

	procedure TAP_test
		(signal usb_d : inout std_logic_vector(7 downto 0);
		 signal usb_rd_n : in std_logic;
		 signal usb_rxf_n : out std_logic;
		 signal usb_wr : in std_logic;
		 signal usb_txe_n : out std_logic) is
	variable d : std_logic_vector(7 downto 0);
	begin
		--=== write buffer test ===
		-- write 4 to COUNT
		usb_out("10010000", usb_d, usb_rd_n, usb_rxf_n);
		usb_out("00000100", usb_d, usb_rd_n, usb_rxf_n);
		-- command buf write, write 4 bytes
		usb_out("00100000", usb_d, usb_rd_n, usb_rxf_n);
		for cnt in 0 to 3 loop
			usb_out("10101010", usb_d, usb_rd_n, usb_rxf_n);
		end loop;

		--=== JTAG run test ===
		-- write 2 to BITS
		usb_out("10110000", usb_d, usb_rd_n, usb_rxf_n);
		usb_out("00000010", usb_d, usb_rd_n, usb_rxf_n);
		-- write pattern to TMS
		usb_out("10101101", usb_d, usb_rd_n, usb_rxf_n);
		usb_out("00000001", usb_d, usb_rd_n, usb_rxf_n);
		-- go!
		usb_out("01000011", usb_d, usb_rd_n, usb_rxf_n);

		-- jtag status test
		while true loop
			usb_out("00010000", usb_d, usb_rd_n, usb_rxf_n);
			usb_in(usb_d, usb_wr, usb_txe_n, d);
			exit when d(0) = '0';
		end loop;

		--=== read buffer test ===
		-- write 4 to COUNT
		usb_out("10010000", usb_d, usb_rd_n, usb_rxf_n);
		usb_out("00000100", usb_d, usb_rd_n, usb_rxf_n);
		-- write 0 to ADDR
		usb_out("11000000", usb_d, usb_rd_n, usb_rxf_n);
		usb_out("00000000", usb_d, usb_rd_n, usb_rxf_n);
		-- command buf read
		usb_out("00110000", usb_d, usb_rd_n, usb_rxf_n);
		-- now 4 bytes come in...
		for cnt in 0 to 3 loop
			usb_in(usb_d, usb_wr, usb_txe_n, d);
			assert ((cnt = 0) and (d = "00000010")) or
					 ((cnt /= 0) and (d = "00000000"));
		end loop;
	end procedure;

	SIGNAL clk :  std_logic;
	SIGNAL usb_d :  std_logic_vector(7 downto 0);
	SIGNAL usb_rd_n :  std_logic;
	SIGNAL usb_wr :  std_logic;
	SIGNAL usb_txe_n :  std_logic;
	SIGNAL usb_rxf_n :  std_logic;
	SIGNAL usb_si :  std_logic;
	SIGNAL jtag_tck_A :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_tck_B :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_tck_fb :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_tdo :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_tdi :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_tms :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_trst_n :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_rst_n :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL jtag_dint :  std_logic_vector(0 to NUM_TAPS-1);
	SIGNAL LEDs : std_logic_vector(3 downto 0);
	SIGNAL jtag_extra : std_logic_vector(0 to 7);
--	SIGNAL debug1: integer range 0 to 31;
	SIGNAL debug1 : std_logic_vector(4 downto 0);

BEGIN

	uut: jtag_controller
		port map
			(
			clk => clk,
			usb_d => usb_d,
			usb_rd_n => usb_rd_n,
			usb_wr => usb_wr,
			usb_txe_n => usb_txe_n,
			usb_rxf_n => usb_rxf_n,
			usb_si => usb_si,
			jtag_tck_A => jtag_tck_A,
			jtag_tck_B => jtag_tck_B,
			jtag_tck_fb => jtag_tck_fb,
			jtag_tdo => jtag_tdo,
			jtag_tdi => jtag_tdi,
			jtag_tms => jtag_tms,
			jtag_trst_n => jtag_trst_n,
			jtag_rst_n => jtag_rst_n,
			jtag_dint => jtag_dint,
			jtag_vgnd => open,
			LEDs => LEDs,
			jtag_extra => jtag_extra,
			debug1 => debug1,
			reconfigure => open
			);


-- *** Test Bench - User Defined Section ***
	
	gfb: for tap in 0 to NUM_TAPS-1 generate
	signal op : std_logic_vector(0 to 1);
	begin
		
		op <= (jtag_tck_A(tap) & jtag_tck_B(tap));

		process (op)
		begin
			case op is

				when "11" | "1Z" | "Z1" =>
					jtag_tck_fb(tap) <= '1' after 0.25 ns;

				when "0Z" | "Z0" =>
					jtag_tck_fb(tap) <= '0' after 0.25 ns;

				when "ZZ" =>
					jtag_tck_fb(tap) <= 'Z' after 0.25 ns;

				when others =>
					jtag_tck_fb(tap) <= 'U' after 0.25 ns;

			end case;
		end process;

	end generate;

	clock_gen : process
	begin
		while true loop
			clk <= '1';
			wait for 10.41666 ns;
			clk <= '0';
			wait for 10.41666 ns;
		end loop;
	end process;

	jtag_tdi <= jtag_tdo after 4 ns;

   tb : PROCESS
   BEGIN
		usb_txe_n <= '0';
		usb_rxf_n <= '1';
		usb_d <= (others => 'Z');


		wait for 1 us;

		-- blink LEDs
		--usb_out("01101110", usb_d, usb_rd_n, usb_rxf_n);
		--usb_out("01101101", usb_d, usb_rd_n, usb_rxf_n);
		--usb_out("01101011", usb_d, usb_rd_n, usb_rxf_n);
		--usb_out("01100111", usb_d, usb_rd_n, usb_rxf_n);
		--usb_out("01101111", usb_d, usb_rd_n, usb_rxf_n);

		-- test TAP 0
		usb_out("00000000", usb_d, usb_rd_n, usb_rxf_n);
		TAP_test(usb_d, usb_rd_n, usb_rxf_n, usb_wr, usb_txe_n);
		 -- and at a lower tck rate
		usb_out("11110011", usb_d, usb_rd_n, usb_rxf_n);
		usb_out("00000101", usb_d, usb_rd_n, usb_rxf_n);
		TAP_test(usb_d, usb_rd_n, usb_rxf_n, usb_wr, usb_txe_n);

		-- test TAP 1
		usb_out("00000001", usb_d, usb_rd_n, usb_rxf_n);
		TAP_test(usb_d, usb_rd_n, usb_rxf_n, usb_wr, usb_txe_n);

		wait;
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;