tag2.npl

Xilinx_usb_jtag 下载器原理图及程序

JDF F
// Created by Project Navigator ver 1.0
PROJECT tag2
DESIGN tag2 Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s30
DEVICETIME 1057171438
DEVPKG tq144
DEVPKGTIME 1052500257
DEVSPEED -5
DEVSPEEDTIME 0
FLOW XST VHDL
FLOWTIME 0
STIMULUS testbench.vhd Normal
MODULE sync.vhd
MODSTYLE sync Normal
MODULE TAP.vhd
MODSTYLE tap Normal
MODULE clkmux.vhd
MODSTYLE clkmux Normal
MODULE tag2.vhd
MODSTYLE jtag_controller Normal
DEPASSOC jtag_controller tag2.ucf Normal
[Normal]
p_ModelSimSimMode=xstvhd, spartan2, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1056312741, Typical Delay
p_ModelSimSimRunTime_tb=xstvhd, spartan2, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1056203187, 0 us
p_ModelSimStructWin=xstvhd, spartan2, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1056203227, False
p_SimModelSelOutBehav=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1056145457, True
p_xstCrossClockAnalysis=xstvhd, spartan2, Schematic.t_synthesize, 1057575873, True
xilxBitgCfg_GenOpt_Compress=xstvhd, spartan2, Implementation.t_bitFile, 1056332136, True
xilxBitgCfg_GenOpt_DRC=xstvhd, spartan2, Implementation.t_bitFile, 1057344562, False
xilxMapTimingDrivenPacking=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1057343663, True
xilxPAReffortLevel=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1056729146, Normal
xilxPostTrceAdvAna=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1056204759, True
xilxPostTrceSkew=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1056204759, True
[STRATEGY-LIST]
Normal=True