mpcbdm.h

powerpc内核mpc860芯片 linux操作系统下交叉调试程序

{"CMPH",	155 ,"","Comparator H Value Register (data)","UM987"},
{"LCTRL1",	156 ,"CTE|3CTF|6CTG|9CTH|12CRWE|14CRWF|16CSG|18CSH|20SUSG|SUSH|CGBMSK|26CHBMSK|30","Load/Store Support Comparators Control Register","UM990"},
{"LCTRL2",	157 ,"LW0EN|LW0IA|3LW0IADC|LW0LA|6LW0LADC|LW0LD|9LW0LDDC|LW1EN|LW1IA|13LW1IADC|LW1LA|16LW1LADC|LW1LD|19LW1LDDC|BRKNOMSK||28DLW0EN|DLW1EN|SLW0EN|SLW1EN","Load/Store Support AND-OR Control Register","UM991"},
{"ICTRL",	158 ,"CTA|3CTB|6CTC|9CTD|12IW0|14IW1|16IW2|18IW3|20SIW0EN|SIW1EN|SIW2EN|SIW3EN|DIW0EN|DIW1EN|DIW2EN|DIW3EN|IFM|ISCT_SER","Instruction Support Control Register","UM989"},
{"BAR",		159 },
{"TBLR",	268 },
{"TBUR",	269 },
{"SPRG0",	272 },
{"SPRG1",	273 },
{"SPRG2",	274 },
{"SPRG3",	275 },
{"TBLW",	284 },
{"TBUW",	285 },
{"PVR",		287 },
{"IC_CST",	560 ,"IEN||4CMD|7|10CCER1|CCER2|CCER3|","Instruction Cache Control and Status Register","UM200"},
{"IC_ADR",	561 ,"|18Data|Way1||Set|28Word|30","Instruction Cache Address Register","UM202"},
{"IC_DAT",	562 ,"Tag|21|Valid|Locked|LRU|","Instruction Cache Data Port Register","UM202"},
{"DC_CST",	568 ,"DEN|DFWT|LES||CMD|8|10CCER1|CCER2|CCER3|","Data Cache Control an Status Register","UM205"},
{"DC_ADR",	569 ,"|18Cbb|Way1||Set|28","Data Cache Address Register","UM208"},
{"DC_DAT",	570 ,"Tag|21|Valid|Locked|LRU|Modified|","Data Cache Data Port Register","UM209"},
{"DPDR",	630 },
{"DPIR",	631 },
{"IMMR",	638 ,"ISB|16PARTNUM|24MASKNUM","Internal Memory Map Register","UM279"},
{"MI_CTR",	784 ,"GPM|PPM|CIDEF||RSV4I||PPCS||19ITLB_INDX|24","IMMU Control Register","UM242"},
{"MI_AP",	786 ,"GP0|2GP1|4GP2|6GP3|8GP4|10GP5|12GP6|14GP7|16GP8|18GP9|20GP10|22GP11|24GP12|26GP13|28GP14|30GP15","IMMU Access Protection Register","UM250"},
{"MI_EPN",	787 ,"EPN|20|22EV||28ASID", "IMMU Effective Page Number Register","UM244"},
{"MI_TWC",	789 ,"|23APG|G|PS|30|V","IMMU Tablewalk Control Register","UM244"},
{"MI_RPN",	790 ,"RPN|20|PP|28SPS|SH|CI|V","IMMU Real Page Number Register","UM246"},
{"MD_CTR",	792 ,"GPM|PPM|CIDEF|WTDEF|RSV4D|TWAM|PPCS||19DTLB_INDX|24","DMMU Control Register","UM243"},
{"M_CASID",	793 ,"|28CASID","MMU Current Address Space ID Register","UM249"},
{"MD_AP",	794 ,"GP0|2GP1|4GP2|6GP3|8GP4|10GP5|12GP6|14GP7|16GP8|18GP9|20GP10|22GP11|24GP12|26GP13|28GP14|30GP15","DMMU Access Protection Register","UM250"},
{"MD_EPN",	795 ,"EPN|20|22EV||28ASID", "IMMU Effective Page Number Register","UM244"},
{"M_TWB",	796 ,"L1TB|20L1INDX|30","MMU Tablewalk Base Register","UM249"},
{"MD_TWC",	797 ,"L2TB|20|23APG|27G|PS|30WT|V","DMMU Tablewalk Control Register","UM245"},
{"MD_RPN",	798 ,"RPN|20PP|28SPS|SH|CI|V","DMMU Real Page Number Register","UM248"},
{"M_TW",	799 ,0,"MMU Tablewalk Special Register","UM250"},
{"MI_CAM",	816 ,"EPN|20PS|23ASID|27SH|SPV","IMMU CAM Entry Read Register","UM251"},
{"MI_RAM0",	817 ,"RPN|20PS_B|23CI|APG|28SFP","IMMU RAM Entry Read Register 0","UM252"},
{"MI_RAM1",	818 ,"|26UFP|30PV|G","IMMU RAM Entry Read Register 1","UM253"},
{"MD_CAM",	824 ,"EPN|20SPVF|24PS|27SH|ASID","DMMU CAM Entry Read Register","UM254"},
{"MD_RAM0",	825 ,"RPN|20PS|23APGI|27G|WT|CI|","DMMU RAM Entry Read Register 0","UM255"},
{"MD_RAM1",	826 ,"|16RES|C|EVF|SA|23SAT|URP0|UWP0|URP1|UWP1|URP2|UWP2|URP3|UWP3","DMMU RAM Entry Read Register 1","UM256"},
//{"",		(SPRI_MASK|0x0), "","",""},
{"SIUMCR",	(SPRI_MASK|0x000) ,"EARB|EARP|4|8DSHW|DBGC|11DBPC|13|FRC|DLK|OPAR|PNCS|DPC|MPRE|MLRC|22AEME|SEME|BSC|GB5E|B2DD|B3DD|","SIU Module Configuration Register","UM280"},
{"SYPCR",	(SPRI_MASK|0x004), "SWTC|16BMT|24BME||28SWF|SWE|SWRI|SWP","System Protection Control Register","UM283"},
{"SWSR",	(SPRI_MASK|0x00E), "","Software Service Register","UM296"}, /*16bit556CAA39*/
{"SIPEND",	(SPRI_MASK|0x010), "IRQ0|LVL0|IRQ1|LVL1|IRQ2|LVL2|IRQ3|LVL3|IRQ4|LVL4|IRQ5|LVL5|IRQ6|LVL6|IRQ7|LVL7|","SIU Interrupt Pending Register","UM291"},
{"SIMASK",	(SPRI_MASK|0x014), "IRM0|LVM0|IRM1|LVM1|IRM2|LVM2|IRM3|LVM3|IRM4|LVM4|IRM5|LVM5|IRM6|LVM6|IRM7|LVM7|","SIU Interrupt Mask Register","UM291"},
{"SIEL",	(SPRI_MASK|0x018), "ED0|WM0|ED1|WM1|ED2|WM2|ED3|WM3|ED4|WM4|ED5|WM5|ED6|WM6|ED7|WM7|","SIU Interrupt Edge/Level Register","UM292"},
{"SIVEC",	(SPRI_MASK|0x01c), "INTC|8","SIU Interrupt Vector Register","UM293"},
{"TESR",	(SPRI_MASK|0x020), "|18IEXT|ITMT|IPB0|IPB1|IPB2|IPB3||26DEXT|DTMT|DPB0|DPB1|DPB2|DPB3","Transfer Error Status Register","UM284"},
{"SDCR",	(SPRI_MASK|0x032), "|17FRZ|19|25AM||30RAID","SDMA Configuration Register","UM570"},
{"PBR0",	(SPRI_MASK|0x080), "","PCMCIA Base Register 0","UM516"},
{"POR0",	(SPRI_MASK|0x084), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 0","UM517"},
{"PBR1",	(SPRI_MASK|0x088), "","PCMCIA Base Register 1","UM516"},
{"POR1",	(SPRI_MASK|0x08C), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 1","UM517"},
{"PBR2",	(SPRI_MASK|0x090), "","PCMCIA Base Register 2","UM516"},
{"POR2",	(SPRI_MASK|0x094), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 2","UM517"},
{"PBR3",	(SPRI_MASK|0x098), "","PCMCIA Base Register 3","UM516"},
{"POR3",	(SPRI_MASK|0x09C), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 3","UM517"},
{"PBR4",	(SPRI_MASK|0x0A0), "","PCMCIA Base Register 4","UM516"},
{"POR4",	(SPRI_MASK|0x0A4), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 4","UM517"},
{"PBR5",	(SPRI_MASK|0x0A8), "","PCMCIA Base Register 5","UM516"},
{"POR5",	(SPRI_MASK|0x0AC), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 5","UM517"},
{"PBR6",	(SPRI_MASK|0x0B0), "","PCMCIA Base Register 6","UM516"},
{"POR6",	(SPRI_MASK|0x0B4), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 6","UM517"},
{"PBR7",	(SPRI_MASK|0x0B8), "","PCMCIA Base Register 7","UM516"},
{"POR7",	(SPRI_MASK|0x0BC), "BSIZE|5|12PSHT|16PSST|20PSL|25PPS|PRS|29PSLOT|WP|PV","PCMCIA Option Register 7","UM517"},
{"PGCRA",	(SPRI_MASK|0x0E0), "CxIREQLVL|8CxSCHLVL|16CxDREQ|18|24CxOE|CxReset|","PCMCIA Interface General Control Register","UM516"},
{"PGCRB",	(SPRI_MASK|0x0E4), "CxIREQLVL|8CxSCHLVL|16CxDREQ|18|24CxOE|CxReset|","PCMCIA Interface General Control Register","UM516"},
{"PSCR",	(SPRI_MASK|0x0E8), "CAVS1_C|CAVS2_C|CAWP_C|CACD2_C|CACD1_C|CABVD2_C|CABVD1_C||CARDY_L|CARDY_H|CARDY_R|CARDY_F||16CBVS1_C|CBVS2_C|CBWP_C|CBCD2_C|CBCD1_C|CBBVD2_C|CBBVD1_C||CBRDY_L|CBRDY_H|CBRDY_R|CBRDY_F|","PCMCIA Interface Status Changed Register","UM513"},
{"PIPR",	(SPRI_MASK|0x0F0), "CAVS1|CAVS2|CAWP|CACD2|CACD1|CABVD2|CABVD1|CARDY||16CBVS1|CBVS2|CBWP|CBCD2|CBCD1|CBBVD2|CBBVD1|CBRDY|","PCMCIA Interface Input Pins Register","UM512"},
{"PER",		(SPRI_MASK|0x0F8), "CA_EVS1_C|CA_EVS2_C|CA_EWP_C|CA_ECD2_C|CA_ECD1_C|CA_EBVD2_C|CA_EBVD1_C||CA_ERDY_L|CA_ERDY_H|CA_ERDY_R|CA_ERDY_F||16CB_EVS1_C|CB_EVS2_C|CB_EWP_C|CB_ECD2_C|CB_ECD1_C|CB_EBVD2_C|CB_EBVD1_C||CB_ERDY_L|CB_ERDY_H|CB_ERDY_R|CB_ERDY_F|","PCMCIA Interface Enable Register","UM514"},
{"BR0",		(SPRI_MASK|0x100), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 0","UM435"},
{"OR0", 	(SPRI_MASK|0x104), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 0","UM437"},
{"BR1",		(SPRI_MASK|0x108), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 1","UM435"},
{"OR1", 	(SPRI_MASK|0x10c), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 1","UM437"},
{"BR2",		(SPRI_MASK|0x110), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 2","UM435"},
{"OR2", 	(SPRI_MASK|0x114), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 2","UM437"},
{"BR3",		(SPRI_MASK|0x118), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 3","UM435"},
{"OR3", 	(SPRI_MASK|0x11c), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 3","UM437"},
{"BR4",		(SPRI_MASK|0x120), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 4","UM435"},
{"OR4", 	(SPRI_MASK|0x124), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 4","UM437"},
{"BR5",		(SPRI_MASK|0x128), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 5","UM435"},
{"OR5", 	(SPRI_MASK|0x12c), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 5","UM437"},
{"BR6",		(SPRI_MASK|0x130), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 6","UM435"},
{"OR6", 	(SPRI_MASK|0x134), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 6","UM437"},
{"BR7",		(SPRI_MASK|0x138), "BA|17AT|20PS|22PARE|WP|MS|26|31V","Base Register 7","UM435"},
{"OR7", 	(SPRI_MASK|0x13c), "AM|17ATM|20CSNT/SAM|ACS/G5LA,G5LS|23BIH|SCY|28SETA|TRLX|EHTR|","Option Register 7","UM437"},
{"MAR",		(SPRI_MASK|0x164), "", "Memory Address Register","UM443"},
{"MCR",		(SPRI_MASK|0x168), "OP|2|8UM||16MB|19|MCLF|24|26MAD","Memory Command Register","UM441"},
{"MAMR",	(SPRI_MASK|0x170), "PTA|8PTAE|AMA|12|DSA|15|G0CLA|19GPLA4DIS|RLFA|24WLFA|28TLFA","Machine A Mode Register","UM440"},
{"MBMR",	(SPRI_MASK|0x174), "PTB|8PTBE|AMB|12|DSB|15|G0CLB|19GPLB4DIS|RLFB|24WLFB|28TLFB","Machine B Mode Register","UM440"},
{"MSTAT",	(SPRI_MASK|0x178), "PER0|PER1|PER2|PER3|PER4|PER5|PER6|PER7|WPER||16PTP|24","Memory Status Register & Periodic Timer","UM439"}, /*contains both MSTAT,MPTPR*/
{"MDR",		(SPRI_MASK|0x17C), "CST4|CST1|CST2|CST3|BST4|BST1|BST2|BST3|G0L|10G0H|12G1T4|G1T3|G2T4|G2T3|G3T4|G3T3|G4T4/DLT3|G4T3/WAEN|G5T4|G5T3||24LOOP|EXEN|AMX|28NA|UTA|TODT|LAST", "Memory Data Register", "UM442"},
{"TBSCR",	(SPRI_MASK|0x200), "TBIRQ|8REFA|REFB||12REFAE|REFBE|TBF|TBE|","Timebase Status and Control Register","UM300"}, /*16bit!*/
{"TBREFA",	(SPRI_MASK|0x204), "","Timebase Reference Register A","UM299"},
{"TBREFB",	(SPRI_MASK|0x208), "","Timebase Reference Register B","UM299"},
{"RTCSC",	(SPRI_MASK|0x220), "RTCIRQ|8SEC|ALR||teK|SIE|ALE|RTF|RTE|","Real-Time Clock Status and Control Register","UM301"}, /*16bit!, teK = 38K*/
{"RTC",		(SPRI_MASK|0x224), "","Real-Time Clock Register","UM302"},
{"RTSEC",	(SPRI_MASK|0x228), "COUNTER|14","Real-Time Clock Alarm Seconds Register","UM304"},
{"RTCAL",	(SPRI_MASK|0x22C), "","Real-Time Clock Alarm Register","UM303"},
{"PISCR",	(SPRI_MASK|0x240), "PIRQ|8PS||13PIE|PITF|PTE|","Periodic Interrupt Status and Control Register","UM305"}, /*16bit!*/
{"PITC",	(SPRI_MASK|0x244), "PITC|16","PIT Count Register","UM306"},
{"PITR",	(SPRI_MASK|0x248), "PIT|16","PIT Register","UM307"},
{"SCCR",	(SPRI_MASK|0x280), "|COM|3|6TBS|RTDIV|RTSEL|CRQEN|PRQEN||13EBDF|15|17DFSYNC|19DFBRG|21DFNL|24DFNH|27","System Clock and Reset Control Register","UM421"},
{"PLPRCR",	(SPRI_MASK|0x284), "MF|12|16SPLSS|TEXPS||TMIST||CSRC|LPM|24CSR|LOLRE|FIOPD|","PLL, Low-Power and Reset Control Register","UM423"},
{"RSR",		(SPRI_MASK|0x288), "EHRS|ESRS|LLRS|SWRS|CSRS|DBHRS|DBSRS|JTRS|","Reset Status Register","UM313"},
{"TBSCRK",	(SPRI_MASK|0x300), "","Timebase Status and Control Register Key","UM285"},
{"CIVR",	(SPRI_MASK|0x930), "VN|5|15IACK|","CPM Interrupt Vector Register 16 bit","UM912"}, /*16bit!*/
{"CICR",	(SPRI_MASK|0x940), "|8SCdP|10SCcP|12SCbP|14SCaP|16IRL|19HP|24IEN||31SPS","CPM Interrupt Configuration Register","UM909"},
{"CIPR",	(SPRI_MASK|0x944), "PC15|SCC1|SCC2|SCC3|SCC4|PC14|TIMER1|PC13|PC12|SDMA|IDMA1|IDMA2||TIMER2|RTT|I2C|PC11|PC10||TIMER3|PC9|PC8|PC7||TIMER4|PC6|SPI|SMC1|SMC2|PC5|PC4|","CPM Interrupt Pending Register","UM910"},
{"CIMR",	(SPRI_MASK|0x948), "PC15|SCC1|SCC2|SCC3|SCC4|PC14|TIMER1|PC13|PC12|SDMA|IDMA1|IDMA2||TIMER2|RTT|I2C|PC11|PC10||TIMER3|PC9|PC8|PC7||TIMER4|PC6|SPI|SMC1|SMC2|PC5|PC4|","CPM Interrupt Mask Register","UM910"},
{"CISR",	(SPRI_MASK|0x94C), "PC15|SCC1|SCC2|SCC3|SCC4|PC14|TIMER1|PC13|PC12|SDMA|IDMA1|IDMA2||TIMER2|RTT|I2C|PC11|PC10||TIMER3|PC9|PC8|PC7||TIMER4|PC6|SPI|SMC1|SMC2|PC5|PC4|","CPM Interrupt In-Service Register","UM910"},
{"PADIR",	(SPRI_MASK|0x950), "DIR|16PAR","Port A Data Direction Register 16 bit",""}, /*16bit! PAPAR*/
{"PAODR",	(SPRI_MASK|0x954), "ODR|16DAT","Port A Open-Drain Register 16 bit",""}, /*16bit! PADAT*/
{"PCDIR",	(SPRI_MASK|0x960), "DIR|16PAR","Port C Data Direction Register 16 bit",""}, /*16bit! PCPAR*/
{"PCSO",	(SPRI_MASK|0x964), "SO|16DAT","Port C Special Option Register 16 bit",""}, /*16bit! PCDAT*/
{"PCINT",	(SPRI_MASK|0x968), "INT|16","Port C Interrupt Control Register 16 bit",""}, /*16bit!*/
{"PDDIR",	(SPRI_MASK|0x970), "DIR|16PAR","Port C Data Direction Register 16 bit",""}, /*16bit! PDPAR*/
{"PDDAT",	(SPRI_MASK|0x976), "ODR|16","Port C Data Register 16 bit",""}, /*16bit!*/
{"PBDIR",	(SPRI_MASK|0xAB8), "","Port B Data Direction Register","UM893"},
{"PBPAR",	(SPRI_MASK|0xABC), "","Port B Pin Assignment Register","UM893"},
{"PBODR",	(SPRI_MASK|0xAC0), "","Port B Open-Drain Register","UM891"},
{"PBDAT",	(SPRI_MASK|0xAC4), "","Port B Data Register","UM892"},
{"SIMODE",	(SPRI_MASK|0xAE0), "SMC2|SMC2CS|4SDMb|6RFSDb|8DSCb|CRTb|STZb|CEb|FEb|GMb|TFSDb|16SMC1|SMC1CS|20SDMa|22RFSDa|24DSCa|CRTa|STZa|CEa|FEa|GMa|TFSDa","SI mode register","UM606"},
{"SIGMR",	(SPRI_MASK|0xAE4), "|4ENb|ENa|RDM|8|16CRORa|CROTa|CRORb|CROTb||24CSRRa|CSRTa|CSRRb|CSRTb|","SI global mode register 8 bit","UM605"}, /*8bit! res, SISTR, SICMR*/
{"SICR",	(SPRI_MASK|0xAEC), "GR4|SC4|R4CS|5T4CS|8GR3|SC3|R3CS|13T3CS|16GR2|SC2|R2CS|21T2CS|24GR1|SC1|R1CS|28T1CS","SI clock route register","UM612"},
{"SIRP",	(SPRI_MASK|0xAF0), "|2VTb|TbPTR|8|10VTa|TaPTR|16|18VRb|RbPTR|24|26VRa|RaPTR","SI RAM pointer register","UM614"},
{"MSR",		(SPR_MASK|0x1), "|13POW||ILE|EE|PR|FP|ME||SE|BE||25IP|IR|DR||30RI|LE","Machine State Register","UM145"},
{"CR",		(SPR_MASK|0x2), "CR0|4CR1|8CR2|12CR3|16CR4|20CR5|24CR6|28CR7","Condition Register","UM140"},
{0 /*last entry for sprnames*/}
};

#define SRR1_MASK 0x9002

#define BDM_NUM_REGS 24

#define BDM_REGMAP \
	GPR_REG_MASK|0,  GPR_REG_MASK|1,  GPR_REG_MASK|2,  GPR_REG_MASK|3,  GPR_REG_MASK|4,  GPR_REG_MASK|5,  GPR_REG_MASK|6,  GPR_REG_MASK|7,  /* r0-r7 */ \
	GPR_REG_MASK|8,  GPR_REG_MASK|9,  GPR_REG_MASK|10, GPR_REG_MASK|11, GPR_REG_MASK|12, GPR_REG_MASK|13, GPR_REG_MASK|14, GPR_REG_MASK|15, /* r8-r15 */ \
	GPR_REG_MASK|16, GPR_REG_MASK|17, GPR_REG_MASK|18, GPR_REG_MASK|19, GPR_REG_MASK|20, GPR_REG_MASK|21, GPR_REG_MASK|22, GPR_REG_MASK|23, /* r16-r23 */ \
	GPR_REG_MASK|24, GPR_REG_MASK|25, GPR_REG_MASK|26, GPR_REG_MASK|27, GPR_REG_MASK|28, GPR_REG_MASK|29, GPR_REG_MASK|30, GPR_REG_MASK|31, /* r24-r31 */ \
\
	2080, 2082, 2084, 2086, 2088, 2090, 2092, 2094, /* fp0->fp8 */ \
	2096, 2098, 2100, 2102, 2104, 2106, 2108, 2110, /* fp0->fp8 */ \
	2112, 2114, 2116, 2118, 2120, 2122, 2124, 2126, /* fp0->fp8 */ \
	2128, 2130, 2132, 2134, 2136, 2138, 2140, 2142, /* fp0->fp8 */ \
\
	SPR_SRR0,     /* pc (SRR0 (SPR 26)) */ \
	SPR_MSR,      /* ps (MSR) */ \
	SPR_CR,       /* cnd (CR) */ \
	SPR_LR,       /* lr (SPR 8) */ \
	SPR_CTR,      /* cnt (CTR (SPR 9)) */ \
	SPR_XER,      /* xer (SPR 1) */ \
	0,            /* mq (SPR 0) */

/*

i86 parallel port registers and pin connections:

|Funct.| Addr.|Access|Bit 7 |Bit 6 |Bit 5 |Bit 4 |Bit 3 |Bit 2 |Bit 1 |Bit 0 |
+------+------+------+------+------+------+------+------+------+------+------+
| DATA |0x378 | R/W  |D7    |D6    |D5    |D4    |D3    |D2    |D1    |D0    |
|      |      |      |Pin 9 |Pin 8 |Pin 7 |Pin 6 |Pin 5 |Pin 4 |Pin 3 |Pin 2 |
|      |      |      |      |      |      |      |      |      |      |      |
+------+------+------+------+------+------+------+------+------+------+------+
| STAT |0x379 |  R   |~Busy | Ack  |PapErr|Select|Error |  1   |  1   |Time- |
|      |      |      |Pin 11|Pin 10|Pin 12| -In  |Pin 15|      |      | out  |
|      |      |      |      |      |      |Pin 13|      |      |      |      |
+------+------+------+------+------+------+------+------+------+------+------+
| CTRL |0x37A |  W   |  1   |   1  |DATDIR|IRQEna|~Se