mpcbdm.h

powerpc内核mpc860芯片 linux操作系统下交叉调试程序

#ifndef _MPCBDM_H_
#define _MPCBDM_H_

#define MAXBUFFERLEN 256		/* needs to be at least word aligned!*/
#define MAXFLASHBANKS 4
#define MAXFLASHSECTORS 1024
#define MAXFLASHCYCLES 10		/* using maximum 2*10 ppc registers for flash preload*/
#define MAXFLASHPRG 100

#define PPC_BITS	32
#define PPC_BIT(x) (1 << (PPC_BITS-1-(x)))

// Commands of Development Port Shift Register

#define DSDI_PREF3_CORE_INSTRUCTION	0x4	// +32 bits
#define DSDI_PREF3_CORE_DATA		0x5	// +32 bits
#define DSDI_PREF3_TECR			0x6	// +7 bits
#define DSDI_PREF3_DPC			0x7	// +7 bits

#define DSDI_DPC_NOP 			0
#define DSDI_DPC_HRESET			0x1
#define DSDI_DPC_SRESET			0x2
#define DSDI_DPC_END_DOWNLOAD		0x43
#define DSDI_DPC_START_DOWNLOAD		0x63
#define DSDI_DPC_NEGATE_MASK_BREAK	0x1f
#define DSDI_DPC_ASSERT_MASK_BREAK	0x3f
#define DSDI_DPC_NEGATE_NMASK_BREAK	0x1f
#define DSDI_DPC_ASSERT_NMASK_BREAK	0x7f

#define DSDO_CORE_DATA		0x0	// +32 bits
#define DSDO_SEQ_ERROR		0x1	// +2 bits + xx
#define DSDO_CORE_INTERRUPT	0x2	// +2 bits + xx
#define DSDO_NULL		0x3	// +2 bits + xx


#define DSDI_COM_NOP  	0x60000000
#define DSDI_COM_RFI  	0x4C000064
#define DSDI_COM_ICR  	0x7C1422A6
#define DSDI_COM_DER  	0x7C1522A6
#define DSDI_COM_MFMSR  0x7C0000A6
#define DSDI_COM_MTSPR  0x7C169BA6

#define GPR_REG_MASK	0x2000

#define SPR_XER		1
#define SPR_LR		8
#define SPR_CTR		9
#define SPR_TBLR	268
#define SPR_TBUR	269
#define SPR_DSISR	18
#define SPR_DAR		19
#define SPR_DEC		22
#define SPR_SRR0	26
#define SPR_SRR1	27
#define SPR_SPRG0	272
#define SPR_SPRG1	273
#define SPR_SPRG2	274
#define SPR_SPRG3	275
#define SPR_TBLW	284
#define SPR_TBUW	285
#define SPR_PVR		287
#define SPR_EIE		80
#define SPR_EID		81
#define SPR_NRI		82
#define SPR_DPIR	631
#define SPR_IMMR	638
#define SPR_IC_CST	560
#define SPR_IC_ADR	561
#define SPR_IC_DAT	562
#define SPR_DC_CST	568
#define SPR_DC_ADR	569
#define SPR_DC_DAT	570
#define SPR_MI_CTR	784
#define SPR_MI_AP	786
#define SPR_MI_EPN	787
#define SPR_MI_TWC	789
#define SPR_MI_RPN	790
#define SPR_MI_CAM	816
#define SPR_MI_RAM0	817
#define SPR_MI_RAM1	818
#define SPR_MD_CTR	792
#define SPR_M_CASID	793
#define SPR_MD_AP	794
#define SPR_MD_EPN	795
#define SPR_M_TWB	796
#define SPR_MD_TWC	797
#define SPR_MD_RPN	798
#define SPR_M_TW	799
#define SPR_MD_CAM	824
#define SPR_MD_RAM0	825
#define SPR_MD_RAM1	826
#define SPR_CMPA	144
#define SPR_CMPB	145
#define SPR_CMPC	146
#define SPR_CMPD	147
#define SPR_ICR		148
#define SPR_DER		149
#define SPR_COUNTA	150
#define SPR_COUNTB	151
#define SPR_CMPE	152
#define SPR_CMPF	153
#define SPR_CMPG	154
#define SPR_CMPH	155
#define SPR_LCTRL1	156
#define SPR_LCTRL2	157
#define SPR_ICTRL	158
#define SPR_BAR		159
#define SPR_DPDR	630

#define SPRI_REV_NUM 0x3cb0

#define SPRI_MASK	0x10000
#define SPRI_SIUMCR	(SPRI_MASK | 0x000)
#define SPRI_SYPCR	(SPRI_MASK | 0x004)
#define SPRI_SWSR	(SPRI_MASK | 0x00E)  /* 16 bit 556C AA39 */
#define SPRI_SCCR	(SPRI_MASK | 0x280)
#define SPRI_PLPRCR	(SPRI_MASK | 0x284)
#define SPRI_RSR	(SPRI_MASK | 0x288)
#define SPRI_BRx(x)	(SPRI_MASK | (0x100 + (x)*8))
#define SPRI_ORx(x)	(SPRI_MASK | (0x104 + (x)*8))
#define SPRI_MAMR	(SPRI_MASK | 0x170)
#define SPRI_MBMR	(SPRI_MASK | 0x174)
#define SPRI_MCR	(SPRI_MASK | 0x168)
#define SPRI_MAR	(SPRI_MASK | 0x164)
#define SPRI_MDR	(SPRI_MASK | 0x17C)
#define SPRI_MSTAT	(SPRI_MASK | 0x178)    /* MSTAT MPTPR */

#define SPR_MASK	0x20000

#define SPR_MSR		(SPR_MASK | 0x1)
#define SPR_CR		(SPR_MASK | 0x2)


#define PPC_I_R0R1   0x90010000   /* stw 0,0(1) # mov r0,@r1 */
#define PPC_I_R0R1hw 0xB0010000    /* stw 0,0(1) # movh r0,@r1 */
#define PPC_I_R1R0   0x80010000   /* lwz 0,0(1) # mov @r1,r0 */

/* from ppc_sprnames.h*/

typedef struct
{
  char *name;	/*motorola name for spr*/
  int num;		/*spr number*/
  char *Namefield; /*(Na|Nb..|Ne) Acronyms of bitfield plus start and end*/
  char *Longname; /*no acronym*/
  char *Reference; /*where to find documentation*/
} SPRNAME;

SPRNAME sprnames[] =
{
{"XER",		1 ,"SO|OV|CA||25BCNT","","UM141"},
{"LR",		8 ,"","Link Register"},
{"CTR",		9 ,"","Counter Register"},
{"DSISR",	18 },
{"DAR",		19 },
{"DEC",		22 ,"","Decrementer Register","UM297"},
{"SRR0",	26 },
{"SRR1",	27 ,"||16EE|PR|FP|ME||SE|BE||26IR|DR||30RI|LE","Machine Status Save/Restore Register1","UM145"},
{"EIE",		80 },
{"EID",		81 },
{"NRI",		82 },
{"CMPA",	144 ,"","Comparator A Value Register (instr)","UM987"},
{"CMPB",	145 ,"","Comparator B Value Register (instr)","UM987"},
{"CMPC",	146 ,"","Comparator C Value Register (instr)","UM987"},
{"CMPD",	147 ,"","Comparator D Value Register (instr)","UM987"},
{"ICR",		148 ,"|RST|CHSTP|MCI||6EXTI|ALI|PRI|FPUVI|DECI||13SYSI|TR||17SEI|ITLBMS|DTBLMS|ITLBER|DTLBER||28LBRK|IBRK|EBRK|DPI","Interrupt Cause Register","UM994"},
{"DER",		149 ,"|RSTE|CHSTPE|MCIE||6EXTIE|ALIE|PRIE|FPUVIE|DECIE||13SYSIE|TRE||17SEIE|ITLBMSE|DTLBMSE|ITLBERE|DTBLERE||28LBRKE|IBRKE|EBRKE|DPIE","Debug Enable Register","UM996"},
{"COUNTA",	150 ,"CNTCV|16|30CNTC","Breakpoint Counter Value and Control A Register","UM994"},
{"COUNTB",	151 ,"CNTCV|16|30CNTC","Breakpoint Counter Value and Control B Register","UM994"},
{"CMPE",	152 ,"","Comparator E Value Register (addr)","UM987"},
{"CMPF",	153 ,"","Comparator F Value Register (addr)","UM987"},
{"CMPG",	154 ,"","Comparator G Value Register (data)","UM987"},