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%-----------------------------------------------------------------------
% Example 7.9.3: RC etwork
%-----------------------------------------------------------------------
clc
clear
q = 101; % number of plot points
T = 10; % upper limit
R = 33; % resistance (ohm)
C = 470.e-6; % capacitance (F)
t = zeros (q,1); % time (sec)
x = zeros (q,1); % capacitor voltage (V)
y = zeros (q,1); % input port voltage (V)
u = zeros (q,1);
n = 10; % number of panels
% Integrand
f = inline ('t.*exp(-t)./(100*(1 + cos(t).^2))','t');
% Compute capacitor and port voltage
fprintf ('Example 7.9.3: RC Network\n');
x(1) = 2.0;
for i = 1 : q
t(i) = (i-1)*T/(q - 1);
u(i) = 1000*f(t(i));
if i > 1
dx = trapint (t(i-1),t(i),n,f);
x(i) = x(i-1) + (1/C)*dx;
end
y(i) = R*f(t(i)) + x(i);
end
% Plot results
graphxy (t,y,'Port Voltage','t (sec)','y (V)');
show ('Final voltage (V)',y(q));
%-----------------------------------------------------------------------
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