📄 pdd.c
字号:
goto clean;
}
m_I2CError = I2C_OK;
clean:
if (m_I2CError != I2C_OK)
DEBUGMSG( ZONE_ERROR || ZONE_I2C, (L"XR20M1170::WriteReg "L"(0x%x) failed\r\n", regaddr));
return m_I2CError;
}
static UCHAR I2c_ReadReg(UARTPDD *pPdd, UCHAR regaddr)
{
UCHAR res;
BOOL m_I2CError = I2C_ERROR;
res = 0;
if (I2CWrite(pPdd->hI2c, ®addr, 1) != 1)
{
DEBUGMSG(ZONE_ERROR || ZONE_I2C,(L"XR20M1170::In ReadReg Write I2c address failed\r\n" ));
goto clean;
}
if (I2CRead(pPdd->hI2c, &res, 1) != 1)
{
DEBUGMSG(ZONE_ERROR || ZONE_I2C,(L"XR20M1170::In ReadReg read failed\r\n" ));
goto clean;
}
m_I2CError = I2C_OK;
//NKDbgPrintfW(_T("I2c_ReadReg: Reg%d, Value:0x%x\r\n"), regaddr/8, res);
clean: ;
if (m_I2CError != I2C_OK)
DEBUGMSG( ZONE_ERROR || ZONE_I2C, (L"XR20M1170::ReadReg "L"(0x%x) failed\r\n", regaddr));
return res;
}
static void gps_poweron(UARTPDD *pPdd, UCHAR on)
{
DEBUGMSG(ZONE_FUNCTION, (L"+/-gps_poweron(%d:%d),IO_CONF6: 0x%x\r\n",
pPdd->gpio_power, on, INREG32(&pPdd->pConfigRegs->IO_CONFIG6)));
if (on) {
GPIOSetBit(pPdd->hGPIO, pPdd->gpio_power);
Sleep(2);
} else {
GPIOClrBit(pPdd->hGPIO, pPdd->gpio_power);
}
}
static void gps_1170_reset(UARTPDD *pPdd)
{
DEBUGMSG(ZONE_FUNCTION, (L"+/-gps_1170_reset(%d)\r\n",pPdd->gpio_reset));
GPIOClrBit(pPdd->hGPIO, pPdd->gpio_reset);
Sleep(200);
GPIOSetBit(pPdd->hGPIO, pPdd->gpio_reset);
}
static void gps_download(UARTPDD *pPdd, UCHAR on)
{
if (on) {
GPIOSetBit(pPdd->hGPIO, pPdd->gpio_download);
} else {
GPIOClrBit(pPdd->hGPIO, pPdd->gpio_download);
}
}
//------------------------------------------------------------------------------
//
// Function: SetAutoRTS
//
// This function enable/disable HW auto RTS.
//
// This function enable/disable auto RTS. It is primary intend to be used
// for BT, but it should work in most cases. However correct function depend
// on oposite device, it must be able to stop sending data in timeframe
// which will not FIFO overflow. Check TCR setting in HWInit.
//
static BOOL SetAutoRTS(UARTPDD *pPdd, BOOL enable)
{
DEBUGMSG(ZONE_FUNCTION, (L"+SetAutoRTS(%x)\r\n",enable));
// Get UART lock
EnterCriticalSection(&pPdd->hwCS);
// Enable/disable hardware auto RTS
if (enable) {
RegSetBit(pPdd, XR20M1170REG_EFR, UART_EFR_AUTO_RTS_EN);
pPdd->autoRTS = TRUE;
} else {
// Disable hardware auto CTS/RTS
RegClrBit(pPdd, XR20M1170REG_EFR, UART_EFR_AUTO_RTS_EN);
pPdd->autoRTS = FALSE;
}
// Free UART lock.
LeaveCriticalSection(&pPdd->hwCS);
DEBUGMSG(ZONE_FUNCTION, (L"-SetAutoRTS()\r\n"));
return TRUE;
}
//------------------------------------------------------------------------------
//
// Function: SetAutoCTS
//
// This function enable/disable HW auto CTS.
//
static BOOL SetAutoCTS(UARTPDD *pPdd, BOOL enable)
{
DEBUGMSG(ZONE_FUNCTION, (L"+SetAutoCTS()\r\n"));
// Get UART lock
EnterCriticalSection(&pPdd->hwCS);
// Enable/disable hardware auto CTS/RTS
if (enable) {
RegSetBit(pPdd, XR20M1170REG_EFR, UART_EFR_AUTO_CTS_EN);
} else {
RegClrBit(pPdd, XR20M1170REG_EFR, UART_EFR_AUTO_CTS_EN);
}
// Free UART lock.
LeaveCriticalSection(&pPdd->hwCS);
DEBUGMSG(ZONE_FUNCTION, (L"-SetAutoCTS()\r\n"));
return TRUE;
}
//------------------------------------------------------------------------------
//
// Function: ReadLineStat
//
// This function reads line status register and it calls back MDD if line
// event occurs. This must be done in this way because register bits are
// cleared on read.
//
static UCHAR ReadLineStat(UARTPDD *pPdd)
{
ULONG events = 0;
UCHAR lineStat;
//DEBUGMSG(ZONE_FUNCTION, (TEXT("+ReadLineStat()\r\n")));
lineStat = RegRead(pPdd, XR20M1170REG_LSR);
if ((lineStat & UART_LSR_RX_FE) != 0)
{
pPdd->commErrors |= CE_FRAME;
events |= EV_ERR;
}
if ((lineStat & UART_LSR_RX_PE) != 0)
{
pPdd->commErrors |= CE_RXPARITY;
events |= EV_ERR;
}
if ((lineStat & UART_LSR_RX_OE) != 0)
{
pPdd->overrunCount++;
pPdd->commErrors |= CE_OVERRUN;
events |= EV_ERR;
}
if ((lineStat & UART_LSR_RX_BI) != 0)
{
events |= EV_BREAK;
}
if ((events & EV_ERR) != 0)
{
DEBUGMSG(ZONE_ERROR, (
L"UART!ReadLineStat: Error detected, LSR: 0x%02x\r\n", lineStat
));
}
// Let MDD know if something happen
if (events != 0) EvaluateEventFlag(pPdd->pMdd, events);
//DEBUGMSG(ZONE_FUNCTION, (TEXT("-ReadLineStat(%02x)\r\n"), lineStat));
return lineStat;
}
//------------------------------------------------------------------------------
//
// Function: ReadModemStat
//
// This function reads modem status register and it calls back MDD if modem
// event occurs. This must be done in this way because register bits are
// cleared on read.
//
static UCHAR ReadModemStat(UARTPDD *pPdd)
{
UCHAR ucModemStat;
ULONG ulEvents;
DEBUGMSG(ZONE_FUNCTION, (L"+ReadModemStat()\r\n"));
// Nothing happen yet...
ulEvents = 0;
// Read line status register (it clear most bits)
ucModemStat = RegRead(pPdd, XR20M1170REG_MSR);
// For changes, we use callback to evaluate the event
if ((ucModemStat & UART_MSR_CTS) != 0) ulEvents |= EV_CTS;
if ((ucModemStat & UART_MSR_DSR) != 0) ulEvents |= EV_DSR;
if ((ucModemStat & UART_MSR_DCD) != 0) ulEvents |= EV_RLSD;
// Let MDD know if something happen
if (ulEvents != 0) EvaluateEventFlag(pPdd->pMdd, ulEvents);
DEBUGMSG(ZONE_FUNCTION, (L"-ReadModemStat()\r\n"));
return ucModemStat;
}
//------------------------------------------------------------------------------
//
// Function: SetBaudRate
//
// This function sets baud rate.
//
static BOOL SetBaudRate(UARTPDD *pPdd, ULONG ulBaudRate)
{
BOOL bRc = FALSE;
UCHAR dlm_reg;
UCHAR dll_reg;
UCHAR dld_reg;
UCHAR prescale;
UCHAR samplemode;
float required_diviser;
float temp;
#if 0
UCHAR reg_val;
reg_val = RegRead( pPdd, XR20M1170REG_MCR);
if(reg_val & 0x90)
prescale = 4;
else
prescale = 1;
reg_val=RegRead( pPdd, XR20M1170REG_DLD);
reg_val &= 0x30;
if(reg_val==0x00) samplemode = 16;
else if (reg_val==0x10) samplemode = 8;
else if (reg_val==0x20) samplemode = 4;
else
{
samplemode = 16;
NKDbgPrintfW(_T("EEROR:DLD[5:4]=0x11\r\n"));
}
#else
prescale = 1; //divide by 1, ReadData(MCR bit 7);
samplemode = 0x10; //16x, ReadData(DLD bit 5:4);
#endif
DEBUGMSG(ZONE_FUNCTION, (L"+SetBaudRate()\r\n"));
temp=(float)prescale*samplemode*ulBaudRate;
required_diviser=(float)pPdd->frequency/temp;
dlm_reg = TRUNC(required_diviser) >> 8;
dll_reg = TRUNC(required_diviser)& 0xff;
dld_reg = ROUND((required_diviser - TRUNC(required_diviser))*16);
#if 0
{
FILE *flt;
flt= fopen("\\My Documents\\debug_gps.txt","a+");
fprintf(flt,"DLM_reg :%x\r\n,DLL_reg :%x\r\n,DLD_reg :%x\r\n", dlm_reg, dll_reg, dld_reg);// write files
fclose(flt);
}
#endif
// Get UART lock.
EnterCriticalSection(&pPdd->hwCS);
// Disable UART? seems not corresponding reg
//now access dll/dlm
RegWrite(pPdd, XR20M1170REG_DLL, dll_reg);
RegWrite(pPdd, XR20M1170REG_DLM, dlm_reg);
RegWrite(pPdd, XR20M1170REG_DLD, dld_reg);
// Enable UART? seems not corresponding reg
// Free UART lock.
LeaveCriticalSection(&pPdd->hwCS);
bRc = TRUE;
//cleanUp:
DEBUGMSG(ZONE_FUNCTION, (L"-SetBaudRate()\r\n"));
return bRc;
}
//------------------------------------------------------------------------------
//
// Function: SetWordLength
//
// This function sets word length.
//
static BOOL SetWordLength(UARTPDD *pPdd, UCHAR ucWordLength)
{
BOOL bRc = FALSE;
UCHAR lcr_reg;
DEBUGMSG(ZONE_FUNCTION, (L"+SetWordLength(%d)\r\n",ucWordLength));
if (ucWordLength < 5 || ucWordLength > 8) goto cleanUp;
EnterCriticalSection(&pPdd->hwCS);
lcr_reg = RegRead(pPdd, XR20M1170REG_LCR);
RegWrite(pPdd, XR20M1170REG_LCR, (lcr_reg & 0xFC) | (ucWordLength - 5));
LeaveCriticalSection(&pPdd->hwCS);
bRc = TRUE;
cleanUp:
DEBUGMSG(ZONE_FUNCTION, (L"-SetWordLength(lcr:%x)\r\n",(lcr_reg & 0xFC) | (ucWordLength - 5)));
return bRc;
}
//------------------------------------------------------------------------------
//
// Function: SetParity
//
// This function sets parity.
//
static BOOL SetParity(UARTPDD *pPdd, UCHAR ucParity)
{
BOOL bRc = FALSE;
UCHAR lcr_reg;
UCHAR ucMask;
DEBUGMSG(ZONE_FUNCTION, (L"+SetParity(0x%x)\r\n",ucParity));
switch (ucParity) {
case NOPARITY:
ucMask = 0;
break;
case ODDPARITY:
ucMask = UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN;
break;
case EVENPARITY:
ucMask = UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN;
break;
default:
goto cleanUp;
}
EnterCriticalSection(&pPdd->hwCS);
lcr_reg = RegRead(pPdd, XR20M1170REG_LCR);
RegWrite(pPdd, XR20M1170REG_LCR, (lcr_reg & 0xC7) | ucMask);
LeaveCriticalSection(&pPdd->hwCS);
bRc = TRUE;
cleanUp:
DEBUGMSG(ZONE_FUNCTION, (L"-SetParity(0x%x)\r\n",(lcr_reg & 0xC7) | ucMask));
return bRc;
}
//------------------------------------------------------------------------------
//
// Function: SetStopBits
//
// This function sets stop bits.
//
static BOOL SetStopBits(UARTPDD *pPdd, UCHAR ucStopBits)
{
BOOL bRc = FALSE;
UCHAR lcr_reg;
UCHAR ucMask;
DEBUGMSG(ZONE_FUNCTION, (L"+SetStopBits(%d)\r\n",ucStopBits));
switch (ucStopBits) {
case ONESTOPBIT:
ucMask = 0;
break;
case ONE5STOPBITS:
case TWOSTOPBITS:
ucMask = UART_LCR_NB_STOP;
break;
default:
goto cleanUp;
}
EnterCriticalSection(&pPdd->hwCS);
lcr_reg = RegRead(pPdd, XR20M1170REG_LCR);
RegWrite(pPdd, XR20M1170REG_LCR, (lcr_reg & 0xFB) | ucMask);
LeaveCriticalSection(&pPdd->hwCS);
bRc = TRUE;
cleanUp:
DEBUGMSG(ZONE_FUNCTION, (L"-SetStopBits()\r\n"));
return bRc;
}
//------------------------------------------------------------------------------
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