📄 ehci.equ
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;***************************************************************************;
;***************************************************************************;
;** **;
;** (C)Copyright 1985-2003, American Megatrends, Inc. **;
;** **;
;** All Rights Reserved. **;
;** **;
;** 6145-F Northbelt Pkwy, Norcross, GA 30071 **;
;** **;
;** Phone (770)-246-8600 **;
;** **;
;***************************************************************************;
;***************************************************************************;
;***************************************************************************;
; $Header: /BIOS/Corebin/800/Modules/USB2/Template/Core/EHCI.EQU 4 3/17/03 5:48p Sivagarn $
;
; $Revision: 4 $
;
; $Date: 3/17/03 5:48p $
;***************************************************************************;
; Revision History
; ----------------
; $Log: /BIOS/Corebin/800/Modules/USB2/Template/Core/EHCI.EQU $
;
; 4 3/17/03 5:48p Sivagarn
; Queue head 'QH128us' is changed to 'QH1ms' in EHCIDescriptors structure
;
; 3 12/17/02 12:32p Sivagarn
; - Code clean up and macros are moved into this file from EHCI.ASM
; - Changed copyright message year to 2003
; - Implemented 128 microsecond polling for interrupt transaction
;
; 2 10/29/02 6:58p Sivagarn
; Flag definition for Async. advance door bell is added
;
; 1 9/15/02 5:39p Sivagarn
; Initial AMIUSB 2.20 check-in
;
;***************************************************************************;
; Global equates for EHCI
;-------------------------------------------------------------------------
MKF_EHCI_64BIT_DATA_STRUCTURE EQU 1
EHCI_FRAMELISTSIZE EQU 1024 ; Number of DWORDs in frame list
; Maximum data that can be transferred in a transaction
MAX_EHCI_DATA_SIZE EQU (16 * 1024)
; Mask for masking unwanted bits in the QH & qTD pointers
EHCI_POINTER_MASK EQU NOT 1Fh ; Mask bit 0-4
; Capability Registers
;-------------------------------------------------------------------------
; These registers specify the limits, restrictions and capabilities of the
; host controller implementation
;-------------------------------------------------------------------------
EHCI_VERCAPLENGTH EQU 00h ; Interface Version and Capability
; Register Length
EHCI_HCSPARAMS EQU 04h ; Structural Parameters
; EHCI_HCSPARAMS bit definitions
EHCI_N_PORTS EQU BIT0+BIT1+BIT2+BIT3 ; Number of implemented
; ports
EHCI_PPC EQU BIT4 ; Port Power Control
EHCI_PRR EQU BIT7 ; Port Routing Rules
EHCI_N_PCC EQU BIT8+BIT9+BIT10+BIT11 ; Number of Ports per
; Companion Controller
EHCI_N_CC EQU BIT12+BIT13+BIT14+BIT15 ; Number of Companion
; Controllers
EHCI_P_INDICATOR EQU BIT16 ; Port Indicators
EHCI_DEBUG_N EQU BIT20+BIT21+BIT22+BIT23 ; Debug Port Number
;---------------------------------------;
EHCI_HCCPARAMS EQU 08h ; Capability Parameters
; EHCI_HCCPARAMS bit definitions
EHCI_64BIT_CAP EQU 0000000000000001B ; 64-bit addressing
; capability
EHCI_PFLFLAG EQU 0000000000000010B ; Programmable Frame
; List Flag
EHCI_ASP_CAP EQU 0000000000000100B ; Asynchronous Schedule
; Park Capability
EHCI_IST EQU 0000000011110000B ; Isochronous Scheduling
; Threshold
EHCI_EECP EQU 1111111100000000B ; EHCI Extended
; Capabilities Pointer
;---------------------------------------;
EHCI_HCSP_PORTROUTE EQU 0Ch ; Companion Port Route Description
; Host Controller operational registers
;-------------------------------------------------------------------------
; The following equates specify the HC operational registers as offsets of
; the operational register base. Operational register base is calculated by
; adding the value in the first capabilities register (EHCI_VERCAPLENGTH) to
; the base address of EHCI HC register address space.
;-------------------------------------------------------------------------
EHCI_USBCMD EQU 00h ; USB Command
; EHCI_USBCMD bit definitions
EHCI_RUNSTOP EQU BIT0
EHCI_HCRESET EQU BIT1
EHCI_FRM1024 EQU 0 ; Reset BIT2 and BIT3 before
EHCI_FRM512 EQU BIT2 ; setting the new Frame List Size
EHCI_FRM256 EQU BIT3
EHCI_PER_SCHED_ENABLE EQU BIT4
EHCI_ASYNC_SCHED_ENABLE EQU BIT5
EHCI_INT_ASYNC_ADVANCE_ENABLE EQU BIT6
EHCI_INTTHRESHOLD EQU (08h SHL 16)
;---------------------------------------;
EHCI_USBSTS EQU 04h ; USB Status
; EHCI_USBSTS bit definitions
EHCI_USB_INTERRUPT EQU BIT0 ; Interrupt
EHCI_USB_ERROR_INTERRUPT EQU BIT1 ; Error interrupt
EHCI_PORT_CHANGE_DETECT EQU BIT2 ; Port Change Detect
EHCI_FRAME_LIST_ROLLOVER EQU BIT3 ; Frame List Rollover
EHCI_HOST_SYSTEM_ERROR EQU BIT4 ; Host System Error
EHCI_INT_ASYNC_ADVANCE EQU BIT5 ; Interrupt on Async Advance
EHCI_HCHALTED EQU BIT12 ; HCHalted
EHCI_RECLAIM EQU BIT13 ; Reclamation
EHCI_PER_SCHED_STATUS EQU BIT14 ; Periodic Schedule Status
EHCI_ASYNC_SCHED_STATUS EQU BIT15 ; Asynchronous Schedule Status
;---------------------------------------;
EHCI_USBINTR EQU 08h ; USB Interrupt Enable
; EHCI_USBINTR bit definitions
EHCI_USBINT_EN EQU BIT0 ; Interrupt Enable
EHCI_USBERRINT_EN EQU BIT1 ; Error Interrupt Enable
EHCI_PCDINT_EN EQU BIT2 ; Port Change Detect Interrupt Enable
EHCI_FLRINT_EN EQU BIT3 ; Frame List Rollover Interrupt Enable
EHCI_HSEINT_EN EQU BIT4 ; Host System Error Interrupt Enable
EHCI_IAAINT_EN EQU BIT5 ; Interrupt on Async Advance Enable
;---------------------------------------;
EHCI_FRINDEX EQU 0Ch ; USB Frame Index
EHCI_CTRLDSSEGMENT EQU 10h ; 4G Segment Selector
EHCI_PERIODICLISTBASE EQU 14h ; Frame List Base Address
EHCI_ASYNCLISTADDR EQU 18h ; Next Asynchronous List Address
EHCI_CONFIGFLAG EQU 40h ; Configured Flag Register
EHCI_PORTSC EQU 44h ; Port Status/Control
; EHCI_PORTSC bit definitions
EHCI_CURRENTCONNECTSTATUS EQU BIT0
EHCI_CONNECTSTATUSCHANGE EQU BIT1
EHCI_PORTENABLE EQU BIT2
EHCI_PORTENABLESTATUSCHANGE EQU BIT3
EHCI_OVERCURRENTACTIVE EQU BIT4
EHCI_OVERCURRENTCAHGE EQU BIT5
EHCI_FORCEPORTRESUME EQU BIT6
EHCI_SUSPEND EQU BIT7
EHCI_PORTRESET EQU BIT8
EHCI_DMINUSBIT EQU BIT10
EHCI_DPLUSBIT EQU BIT11
EHCI_PORTPOWER EQU BIT12
EHCI_PORTOWNER EQU BIT13
EHCI_WKCNNT_E EQU BIT20 ; Wake On Connect Enable
EHCI_WKDSCNNT_E EQU BIT21 ; Wake On Disconnect Enable
EHCI_WKOC_E EQU BIT22 ; Wake On Over-current Enable
;-------------------------------------------------------------------------
; Descriptor structure used to store TD and ED addresses
;-------------------------------------------------------------------------
;
; Bit definitions for a generic pointer
;
EHCI_TERMINATE EQU 000000001h
;<AMI_SHDR_START>
;----------------------------------------------------------------------------
; Name: EHCI_QTD
;
; Description: This is EHCI queue TD data structure used to perform
; non-isochronous transaction in EHCI based HC
;
; Fields: Name Type Description
; ------------------------------------------------------------
; dNextqTDPtr DWORD Pointer to next qTD
; dAltNextqTDPtr DWORD Pointer to alternate next qTD
; dToken DWORD Token double word
; dBufferPtr0 DWORD Buffer pointer page 0
; dBufferPtr1 DWORD Buffer pointer page 1
; dBufferPtr2 DWORD Buffer pointer page 2
; dBufferPtr3 DWORD Buffer pointer page 3
; dBufferPtr4 DWORD Buffer pointer page 4
;
;----------------------------------------------------------------------------
;<AMI_SHDR_END>
EHCI_QTD STRUC
dNextqTDPtr DD ?
dAltNextqTDPtr DD ?
dToken DD ?
dBufferPtr0 DD ?
dBufferPtr1 DD ?
dBufferPtr2 DD ?
dBufferPtr3 DD ?
dBufferPtr4 DD ?
IF MKF_EHCI_64BIT_DATA_STRUCTURE
; For 64bit data structure
dReserved DD 8 dup (?)
ENDIF
EHCI_QTD ENDS
USB_EHCI_QTD_SIZE_BLK EQU ((SIZE EHCI_QTD + \
USB_MEM_BLK_SIZE - 1) SHR \
USB_MEM_BLK_SIZE_SHIFT)
; Queue head call back function prototype
FUNCQHCALLBACK TYPEDEF PROTO NEAR C pHCStruc:NEAR, pQH:NEAR
PTRFUNCQHCALLBACK TYPEDEF PTR FUNCQHCALLBACK
;<AMI_SHDR_START>
;----------------------------------------------------------------------------
; Name: EHCI_QH
;
; Description: This is EHCI queue head data structure used to perform
; non-isochronous transaction in EHCI based HC
;
; Fields: Name Type Description
; ------------------------------------------------------------
; dLinkPointer DWORD Pointer to the next queue head
; dEndPntCharac DWORD Endpoint characteristics settings
; dEndPntCap DWORD Endpoint capability settings
; dCurqTDPtr DWORD Pointer to current qTD
; dNextqTDPtr DWORD Pointer to next qTD
; dAltNextqTDPtr DWORD Pointer to alternate next qTD
; dToken DWORD Token double word
; dBufferPtr0 DWORD Buffer pointer page 0
; dBufferPtr1 DWORD Buffer pointer page 1
; dBufferPtr2 DWORD Buffer pointer page 2
; dBufferPtr3 DWORD Buffer pointer page 3
; dBufferPtr4 DWORD Buffer pointer page 4
;
;----------------------------------------------------------------------------
;<AMI_SHDR_END>
EHCI_QH STRUC
dLinkPointer DD ?
dEndPntCharac DD ?
dEndPntCap DD ?
dCurqTDPtr DD ?
dNextqTDPtr DD ?
dAltNextqTDPtr DD ?
dToken DD ?
dBufferPtr0 DD ?
dBufferPtr1 DD ?
dBufferPtr2 DD ?
dBufferPtr3 DD ?
dBufferPtr4 DD ?
IF MKF_EHCI_64BIT_DATA_STRUCTURE
; For 64bit data structure
dReserved DD 8 dup (?)
ENDIF
pCallBackFunc PTRFUNCQHCALLBACK ?
pFirstqTD DW ?
bActive DB ?
bErrorStatus DB ?
pDevInfoPtr DW ?
aDataBuffer DB 8 dup (?)
EHCI_QH ENDS
USB_EHCI_QH_SIZE_BLK EQU ((SIZE EHCI_QH + \
USB_MEM_BLK_SIZE - 1) SHR \
USB_MEM_BLK_SIZE_SHIFT)
EHCI_QUEUE_HEAD EQU 02h ; Queue head id
; Bit definition for queue transfer descriptor token fields
;-------------------------------------------------------------------------
QTD_DATA_TOGGLE EQU 080000000h ; BIT 31
QTD_SETUP_TOGGLE EQU 000000000h
QTD_DATA0_TOGGLE EQU 000000000h
QTD_DATA1_TOGGLE EQU 080000000h
QTD_STATUS_TOGGLE EQU 080000000h
QTD_XFER_DATA_SIZE EQU 07FFF0000h ; BIT 30:16
QTD_IOC_BIT EQU 000008000h ; BIT 15
QTD_ERROR_COUNT EQU 000000C00h
QTD_NO_ERRORS EQU 000000000h
QTD_ONE_ERROR EQU 000000400h
QTD_TWO_ERRORS EQU 000000800h
QTD_THREE_ERRORS EQU 000000C00h
QTD_DIRECTION_PID EQU 000000300h
QTD_OUT_TOKEN EQU 000000000h
QTD_IN_TOKEN EQU 000000100h
QTD_SETUP_TOKEN EQU 000000200h
QTD_STATUS_FIELD EQU 0000000FFh
QTD_ACTIVE EQU 000000080h
QTD_HALTED EQU 000000040h
QTD_BUFFER_ERROR EQU 000000020h
QTD_BABBLE EQU 000000010h
QTD_XACT_ERROR EQU 000000008h
QTD_MISSED_UFRAME EQU 000000004h
QTD_SPLIT_XSTATE EQU 000000002h
QTD_START_SPLIT EQU 000000000h
QTD_COMPLETE_SPLIT EQU 000000002h
QTD_SPLIT_ERROR EQU 000000001h
QTD_PING_STATE EQU 000000001h
QTD_DO_OUT EQU 000000000h
QTD_DO_PING EQU 000000001h
;-------------------------------------------------------------------------
QH_I_BIT EQU 000000080h ; BIT 7
QH_ENDPOINT_SPEED EQU 000003000h ; BIT 13:12
QH_FULL_SPEED EQU 000000000h
QH_LOW_SPEED EQU 000001000h
QH_HIGH_SPEED EQU 000002000h
QH_DATA_TOGGLE_CONTROL EQU 000004000h ; BIT 14
QH_IGNORE_QTD_DT EQU 000000000h
QH_USE_QTD_DT EQU 000004000h
QH_HEAD_OF_LIST EQU 000008000h ; BIT 15
QH_CONTROL_ENDPOINT EQU 008000000h ; BIT 27
QH_DATA_TOGGLE EQU 080000000h ; BIT 31
QH_MULT_SETTING EQU 0C0000000h ; BIT 31:30
QH_ONE_XFER EQU 040000000h
QH_TWO_XFER EQU 080000000h
QH_THREE_XFER EQU 0C0000000h
;-------------------------------------------------------------------------
; Descriptor structure used to store qTD and QH addresses
;-------------------------------------------------------------------------
EHCIDescriptors STRUC
QH1ms WORD ?
QH8ms WORD ?
QH32ms WORD ?
QHRepeat WORD ?
qTDRepeat WORD ?
QHControl WORD ?
qTDControlSetup WORD ?
qTDControlData WORD ?
qTDControlStatus WORD ?
QHInterrupt WORD ?
qTDInterruptData WORD ?
QHBulk WORD ?
qTDBulkData WORD ?
EHCIDescriptors ENDS
USB_EHCI_DESCRIPTOR_SIZE_BLK EQU ((SIZE EHCIDescriptors + \
USB_MEM_BLK_SIZE - 1) SHR \
USB_MEM_BLK_SIZE_SHIFT)
;-------------------------------------------------------------------------
EHCI_DWORD_READ_MEM MACRO HCSTRUC, MEM_OFFSET
IF MKF_USB_MODE EQ 1
INVOKE EHCIDwordReadMemReg, HCSTRUC, MEM_OFFSET
ELSE
mov eax, DWORD PTR FS:[edi+MEM_OFFSET]
ENDIF
ENDM
EHCI_DWORD_WRITE_MEM MACRO HCSTRUC, MEM_OFFSET, VALUE
IF MKF_USB_MODE EQ 1
INVOKE EHCIDwordWriteMemReg, HCSTRUC, MEM_OFFSET, VALUE
ELSE
mov DWORD PTR FS:[edi+MEM_OFFSET], VALUE
ENDIF
ENDM
EHCI_DWORD_SET_MEM MACRO HCSTRUC, MEM_OFFSET, VALUE
IF MKF_USB_MODE EQ 1
INVOKE EHCIDwordReadMemReg, HCSTRUC, MEM_OFFSET
or eax, VALUE
INVOKE EHCIDwordWriteMemReg, HCSTRUC, MEM_OFFSET, eax
ELSE
or DWORD PTR FS:[edi+MEM_OFFSET], VALUE
ENDIF
ENDM
EHCI_DWORD_RESET_MEM MACRO HCSTRUC, MEM_OFFSET, VALUE
IF MKF_USB_MODE EQ 1
INVOKE EHCIDwordReadMemReg, HCSTRUC, MEM_OFFSET
and eax, NOT VALUE
INVOKE EHCIDwordWriteMemReg, HCSTRUC, MEM_OFFSET, eax
ELSE
and DWORD PTR FS:[edi+MEM_OFFSET], NOT VALUE
ENDIF
ENDM
EHCI_SET_FS_EDI MACRO
IF MKF_USB_MODE NE 1
push fs
push edi
push eax
push 0
pop fs
mov edi, (HCStruc PTR [si]).dBaseAddress
movzx eax, (HCStruc PTR [si]).bOpRegOffset
add edi, eax
pop eax
ENDIF
ENDM
;-------------------------------------------------------------------------
;*****************************************************************;
;*****************************************************************;
;** **;
;** (C)Copyright 1985-2003, American Megatrends, Inc. **;
;** **;
;** All Rights Reserved. **;
;** **;
;** 6145-F Northbelt Pkwy, Norcross, GA 30071 **;
;** **;
;** Phone (770)-246-8600 **;
;** **;
;*****************************************************************;
;*****************************************************************;
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