top.tan.qmsg

串口驱动以及串口调试的源代码

{ "Info" "ITDB_TH_RESULT" "top:inst\|reciever:u2\|state.r_start rxd clk -1.104 ns register " "Info: th for register \"top:inst\|reciever:u2\|state.r_start\" (data pin = \"rxd\", clock pin = \"clk\") is -1.104 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.711 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 48 -8 160 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns top:inst\|baud:u1\|bclk 2 REG LC_X8_Y10_N8 99 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N8; Fanout = 99; REG Node = 'top:inst\|baud:u1\|bclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk top:inst|baud:u1|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "F:/UARTEXAMPLE/baud.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.851 ns) + CELL(0.711 ns) 7.711 ns top:inst\|reciever:u2\|state.r_start 3 REG LC_X22_Y12_N5 3 " "Info: 3: + IC(3.851 ns) + CELL(0.711 ns) = 7.711 ns; Loc. = LC_X22_Y12_N5; Fanout = 3; REG Node = 'top:inst\|reciever:u2\|state.r_start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.562 ns" { top:inst|baud:u1|bclk top:inst|reciever:u2|state.r_start } "NODE_NAME" } } { "reciever.vhd" "" { Text "F:/UARTEXAMPLE/reciever.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.40 % ) " "Info: Total cell delay = 3.115 ns ( 40.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.596 ns ( 59.60 % ) " "Info: Total interconnect delay = 4.596 ns ( 59.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.711 ns" { clk top:inst|baud:u1|bclk top:inst|reciever:u2|state.r_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.711 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|reciever:u2|state.r_start } { 0.000ns 0.000ns 0.745ns 3.851ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "reciever.vhd" "" { Text "F:/UARTEXAMPLE/reciever.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.830 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rxd 1 PIN PIN_132 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_132; Fanout = 13; PIN Node = 'rxd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 128 56 224 144 "rxd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.623 ns) + CELL(0.738 ns) 8.830 ns top:inst\|reciever:u2\|state.r_start 2 REG LC_X22_Y12_N5 3 " "Info: 2: + IC(6.623 ns) + CELL(0.738 ns) = 8.830 ns; Loc. = LC_X22_Y12_N5; Fanout = 3; REG Node = 'top:inst\|reciever:u2\|state.r_start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.361 ns" { rxd top:inst|reciever:u2|state.r_start } "NODE_NAME" } } { "reciever.vhd" "" { Text "F:/UARTEXAMPLE/reciever.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 24.99 % ) " "Info: Total cell delay = 2.207 ns ( 24.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.623 ns ( 75.01 % ) " "Info: Total interconnect delay = 6.623 ns ( 75.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.830 ns" { rxd top:inst|reciever:u2|state.r_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.830 ns" { rxd rxd~out0 top:inst|reciever:u2|state.r_start } { 0.000ns 0.000ns 6.623ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.711 ns" { clk top:inst|baud:u1|bclk top:inst|reciever:u2|state.r_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.711 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|reciever:u2|state.r_start } { 0.000ns 0.000ns 0.745ns 3.851ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.830 ns" { rxd top:inst|reciever:u2|state.r_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.830 ns" { rxd rxd~out0 top:inst|reciever:u2|state.r_start } { 0.000ns 0.000ns 6.623ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 17:40:58 2008 " "Info: Processing ended: Sun Mar 02 17:40:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}