top.tan.qmsg

串口驱动以及串口调试的源代码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "top:inst\|baud:u1\|bclk " "Info: Detected ripple clock \"top:inst\|baud:u1\|bclk\" as buffer" {  } { { "baud.vhd" "" { Text "F:/UARTEXAMPLE/baud.vhd" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "top:inst\|baud:u1\|bclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register top:inst\|transfer:u3\|xbitcnt\[23\] register top:inst\|transfer:u3\|xbitcnt\[0\] 157.88 MHz 6.334 ns Internal " "Info: Clock \"clk\" has Internal fmax of 157.88 MHz between source register \"top:inst\|transfer:u3\|xbitcnt\[23\]\" and destination register \"top:inst\|transfer:u3\|xbitcnt\[0\]\" (period= 6.334 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.073 ns + Longest register register " "Info: + Longest register to register delay is 6.073 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top:inst\|transfer:u3\|xbitcnt\[23\] 1 REG LC_X15_Y10_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y10_N7; Fanout = 4; REG Node = 'top:inst\|transfer:u3\|xbitcnt\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|transfer:u3|xbitcnt[23] } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.755 ns) + CELL(0.590 ns) 1.345 ns top:inst\|transfer:u3\|Equal0~358 2 COMB LC_X14_Y10_N0 1 " "Info: 2: + IC(0.755 ns) + CELL(0.590 ns) = 1.345 ns; Loc. = LC_X14_Y10_N0; Fanout = 1; COMB Node = 'top:inst\|transfer:u3\|Equal0~358'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.345 ns" { top:inst|transfer:u3|xbitcnt[23] top:inst|transfer:u3|Equal0~358 } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.252 ns) + CELL(0.292 ns) 2.889 ns top:inst\|transfer:u3\|Equal0~359 3 COMB LC_X15_Y9_N9 1 " "Info: 3: + IC(1.252 ns) + CELL(0.292 ns) = 2.889 ns; Loc. = LC_X15_Y9_N9; Fanout = 1; COMB Node = 'top:inst\|transfer:u3\|Equal0~359'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.544 ns" { top:inst|transfer:u3|Equal0~358 top:inst|transfer:u3|Equal0~359 } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 3.624 ns top:inst\|transfer:u3\|Equal0~362 4 COMB LC_X15_Y9_N7 3 " "Info: 4: + IC(0.443 ns) + CELL(0.292 ns) = 3.624 ns; Loc. = LC_X15_Y9_N7; Fanout = 3; COMB Node = 'top:inst\|transfer:u3\|Equal0~362'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.735 ns" { top:inst|transfer:u3|Equal0~359 top:inst|transfer:u3|Equal0~362 } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.920 ns top:inst\|transfer:u3\|xbitcnt\[1\]~1460 5 COMB LC_X15_Y9_N8 32 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 3.920 ns; Loc. = LC_X15_Y9_N8; Fanout = 32; COMB Node = 'top:inst\|transfer:u3\|xbitcnt\[1\]~1460'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { top:inst|transfer:u3|Equal0~362 top:inst|transfer:u3|xbitcnt[1]~1460 } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.867 ns) 6.073 ns top:inst\|transfer:u3\|xbitcnt\[0\] 6 REG LC_X15_Y12_N4 6 " "Info: 6: + IC(1.286 ns) + CELL(0.867 ns) = 6.073 ns; Loc. = LC_X15_Y12_N4; Fanout = 6; REG Node = 'top:inst\|transfer:u3\|xbitcnt\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.153 ns" { top:inst|transfer:u3|xbitcnt[1]~1460 top:inst|transfer:u3|xbitcnt[0] } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.155 ns ( 35.48 % ) " "Info: Total cell delay = 2.155 ns ( 35.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.918 ns ( 64.52 % ) " "Info: Total interconnect delay = 3.918 ns ( 64.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.073 ns" { top:inst|transfer:u3|xbitcnt[23] top:inst|transfer:u3|Equal0~358 top:inst|transfer:u3|Equal0~359 top:inst|transfer:u3|Equal0~362 top:inst|transfer:u3|xbitcnt[1]~1460 top:inst|transfer:u3|xbitcnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.073 ns" { top:inst|transfer:u3|xbitcnt[23] top:inst|transfer:u3|Equal0~358 top:inst|transfer:u3|Equal0~359 top:inst|transfer:u3|Equal0~362 top:inst|transfer:u3|xbitcnt[1]~1460 top:inst|transfer:u3|xbitcnt[0] } { 0.000ns 0.755ns 1.252ns 0.443ns 0.182ns 1.286ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.693 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 48 -8 160 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns top:inst\|baud:u1\|bclk 2 REG LC_X8_Y10_N8 99 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N8; Fanout = 99; REG Node = 'top:inst\|baud:u1\|bclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk top:inst|baud:u1|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "F:/UARTEXAMPLE/baud.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.833 ns) + CELL(0.711 ns) 7.693 ns top:inst\|transfer:u3\|xbitcnt\[0\] 3 REG LC_X15_Y12_N4 6 " "Info: 3: + IC(3.833 ns) + CELL(0.711 ns) = 7.693 ns; Loc. = LC_X15_Y12_N4; Fanout = 6; REG Node = 'top:inst\|transfer:u3\|xbitcnt\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.544 ns" { top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[0] } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.49 % ) " "Info: Total cell delay = 3.115 ns ( 40.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.578 ns ( 59.51 % ) " "Info: Total interconnect delay = 4.578 ns ( 59.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[0] } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.693 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 48 -8 160 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns top:inst\|baud:u1\|bclk 2 REG LC_X8_Y10_N8 99 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N8; Fanout = 99; REG Node = 'top:inst\|baud:u1\|bclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk top:inst|baud:u1|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "F:/UARTEXAMPLE/baud.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.833 ns) + CELL(0.711 ns) 7.693 ns top:inst\|transfer:u3\|xbitcnt\[23\] 3 REG LC_X15_Y10_N7 4 " "Info: 3: + IC(3.833 ns) + CELL(0.711 ns) = 7.693 ns; Loc. = LC_X15_Y10_N7; Fanout = 4; REG Node = 'top:inst\|transfer:u3\|xbitcnt\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.544 ns" { top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[23] } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.49 % ) " "Info: Total cell delay = 3.115 ns ( 40.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.578 ns ( 59.51 % ) " "Info: Total interconnect delay = 4.578 ns ( 59.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[23] } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[0] } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[23] } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.073 ns" { top:inst|transfer:u3|xbitcnt[23] top:inst|transfer:u3|Equal0~358 top:inst|transfer:u3|Equal0~359 top:inst|transfer:u3|Equal0~362 top:inst|transfer:u3|xbitcnt[1]~1460 top:inst|transfer:u3|xbitcnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.073 ns" { top:inst|transfer:u3|xbitcnt[23] top:inst|transfer:u3|Equal0~358 top:inst|transfer:u3|Equal0~359 top:inst|transfer:u3|Equal0~362 top:inst|transfer:u3|xbitcnt[1]~1460 top:inst|transfer:u3|xbitcnt[0] } { 0.000ns 0.755ns 1.252ns 0.443ns 0.182ns 1.286ns } { 0.000ns 0.590ns 0.292ns 0.292ns 0.114ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[0] } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|xbitcnt[23] } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "top:inst\|reciever:u2\|\\pro2:rcnt\[26\] rxd clk 3.170 ns register " "Info: tsu for register \"top:inst\|reciever:u2\|\\pro2:rcnt\[26\]\" (data pin = \"rxd\", clock pin = \"clk\") is 3.170 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.844 ns + Longest pin register " "Info: + Longest pin to register delay is 10.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rxd 1 PIN PIN_132 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_132; Fanout = 13; PIN Node = 'rxd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 128 56 224 144 "rxd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.631 ns) + CELL(0.590 ns) 8.690 ns top:inst\|reciever:u2\|\\pro2:rcnt\[15\]~37 2 COMB LC_X22_Y12_N4 32 " "Info: 2: + IC(6.631 ns) + CELL(0.590 ns) = 8.690 ns; Loc. = LC_X22_Y12_N4; Fanout = 32; COMB Node = 'top:inst\|reciever:u2\|\\pro2:rcnt\[15\]~37'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.221 ns" { rxd top:inst|reciever:u2|\pro2:rcnt[15]~37 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.287 ns) + CELL(0.867 ns) 10.844 ns top:inst\|reciever:u2\|\\pro2:rcnt\[26\] 3 REG LC_X23_Y10_N0 4 " "Info: 3: + IC(1.287 ns) + CELL(0.867 ns) = 10.844 ns; Loc. = LC_X23_Y10_N0; Fanout = 4; REG Node = 'top:inst\|reciever:u2\|\\pro2:rcnt\[26\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.154 ns" { top:inst|reciever:u2|\pro2:rcnt[15]~37 top:inst|reciever:u2|\pro2:rcnt[26] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns ( 26.98 % ) " "Info: Total cell delay = 2.926 ns ( 26.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.918 ns ( 73.02 % ) " "Info: Total interconnect delay = 7.918 ns ( 73.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.844 ns" { rxd top:inst|reciever:u2|\pro2:rcnt[15]~37 top:inst|reciever:u2|\pro2:rcnt[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.844 ns" { rxd rxd~out0 top:inst|reciever:u2|\pro2:rcnt[15]~37 top:inst|reciever:u2|\pro2:rcnt[26] } { 0.000ns 0.000ns 6.631ns 1.287ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.711 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 48 -8 160 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns top:inst\|baud:u1\|bclk 2 REG LC_X8_Y10_N8 99 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N8; Fanout = 99; REG Node = 'top:inst\|baud:u1\|bclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk top:inst|baud:u1|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "F:/UARTEXAMPLE/baud.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.851 ns) + CELL(0.711 ns) 7.711 ns top:inst\|reciever:u2\|\\pro2:rcnt\[26\] 3 REG LC_X23_Y10_N0 4 " "Info: 3: + IC(3.851 ns) + CELL(0.711 ns) = 7.711 ns; Loc. = LC_X23_Y10_N0; Fanout = 4; REG Node = 'top:inst\|reciever:u2\|\\pro2:rcnt\[26\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.562 ns" { top:inst|baud:u1|bclk top:inst|reciever:u2|\pro2:rcnt[26] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.40 % ) " "Info: Total cell delay = 3.115 ns ( 40.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.596 ns ( 59.60 % ) " "Info: Total interconnect delay = 4.596 ns ( 59.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.711 ns" { clk top:inst|baud:u1|bclk top:inst|reciever:u2|\pro2:rcnt[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.711 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|reciever:u2|\pro2:rcnt[26] } { 0.000ns 0.000ns 0.745ns 3.851ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.844 ns" { rxd top:inst|reciever:u2|\pro2:rcnt[15]~37 top:inst|reciever:u2|\pro2:rcnt[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.844 ns" { rxd rxd~out0 top:inst|reciever:u2|\pro2:rcnt[15]~37 top:inst|reciever:u2|\pro2:rcnt[26] } { 0.000ns 0.000ns 6.631ns 1.287ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.711 ns" { clk top:inst|baud:u1|bclk top:inst|reciever:u2|\pro2:rcnt[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.711 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|reciever:u2|\pro2:rcnt[26] } { 0.000ns 0.000ns 0.745ns 3.851ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk txd top:inst\|transfer:u3\|txds 13.805 ns register " "Info: tco from clock \"clk\" to destination pin \"txd\" through register \"top:inst\|transfer:u3\|txds\" is 13.805 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.693 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 48 -8 160 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns top:inst\|baud:u1\|bclk 2 REG LC_X8_Y10_N8 99 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N8; Fanout = 99; REG Node = 'top:inst\|baud:u1\|bclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk top:inst|baud:u1|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "F:/UARTEXAMPLE/baud.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.833 ns) + CELL(0.711 ns) 7.693 ns top:inst\|transfer:u3\|txds 3 REG LC_X15_Y12_N3 2 " "Info: 3: + IC(3.833 ns) + CELL(0.711 ns) = 7.693 ns; Loc. = LC_X15_Y12_N3; Fanout = 2; REG Node = 'top:inst\|transfer:u3\|txds'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.544 ns" { top:inst|baud:u1|bclk top:inst|transfer:u3|txds } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.49 % ) " "Info: Total cell delay = 3.115 ns ( 40.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.578 ns ( 59.51 % ) " "Info: Total interconnect delay = 4.578 ns ( 59.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|txds } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|txds } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.888 ns + Longest register pin " "Info: + Longest register to pin delay is 5.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top:inst\|transfer:u3\|txds 1 REG LC_X15_Y12_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y12_N3; Fanout = 2; REG Node = 'top:inst\|transfer:u3\|txds'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { top:inst|transfer:u3|txds } "NODE_NAME" } } { "transfer.vhd" "" { Text "F:/UARTEXAMPLE/transfer.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.764 ns) + CELL(2.124 ns) 5.888 ns txd 2 PIN PIN_131 0 " "Info: 2: + IC(3.764 ns) + CELL(2.124 ns) = 5.888 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'txd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.888 ns" { top:inst|transfer:u3|txds txd } "NODE_NAME" } } { "top1.bdf" "" { Schematic "F:/UARTEXAMPLE/top1.bdf" { { 112 416 592 128 "txd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 36.07 % ) " "Info: Total cell delay = 2.124 ns ( 36.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.764 ns ( 63.93 % ) " "Info: Total interconnect delay = 3.764 ns ( 63.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.888 ns" { top:inst|transfer:u3|txds txd } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.888 ns" { top:inst|transfer:u3|txds txd } { 0.000ns 3.764ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.693 ns" { clk top:inst|baud:u1|bclk top:inst|transfer:u3|txds } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.693 ns" { clk clk~out0 top:inst|baud:u1|bclk top:inst|transfer:u3|txds } { 0.000ns 0.000ns 0.745ns 3.833ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.888 ns" { top:inst|transfer:u3|txds txd } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.888 ns" { top:inst|transfer:u3|txds txd } { 0.000ns 3.764ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}