read_master_dma.v

DE1上avalon总线挂接LCD控制器示例

module read_master_dma(
						master_clk,
						master_reset_n,
						master_read,
						master_address,
						master_waitrequest,
						master_readdatavalid,
						master_readdata,
						dma_source_reg,
						dma_modules_reg,
						dma_writedata,
						dma_writefifo,
						dma_go_bit,
						fifo_has_room,
						clear_the_fifo,
						dma_current_reg,
						//test
						addressCounter_sload,
						addressCounter_incr
						);
input			master_clk;
input			master_reset_n;
output			master_read;
output	[31:0]	master_address;
input			master_waitrequest;
input			master_readdatavalid;
input	[31:0]	master_readdata;
input	[31:0]	dma_source_reg;
input	[31:0]	dma_modules_reg;
input			dma_go_bit;
output	[31:0]	dma_writedata;
output			dma_writefifo;
input			fifo_has_room;
input			clear_the_fifo;
output	[31:0]	dma_current_reg;

output			addressCounter_sload;
output			addressCounter_incr;

reg		[29:0]	addressCounter_temp;
wire	[31:0]	addressCounter;
reg		[31:0]	last_dma_addr_reg;
reg		[31:0]	dma_current_reg;
wire			addressCounter_sload;
wire			addressCounter_incr;

assign	addressCounter[31:0]	=	{addressCounter_temp[29:0],2'b00};
assign	dma_writedata[31:0]		=	master_readdata[31:0];
assign	dma_writefifo			=	dma_go_bit & master_readdatavalid;

assign	addressCounter_sload	=	(dma_go_bit == 0) || (addressCounter_incr && (addressCounter == last_dma_addr_reg)) || clear_the_fifo;
assign	addressCounter_incr		=	(master_read == 1) && (master_waitrequest == 0) && (dma_go_bit == 1);
assign	master_address[31:0]	=	addressCounter[31:0];
assign	master_read				=	dma_go_bit & fifo_has_room;


always @(posedge master_clk or negedge master_reset_n)
begin
	if(master_reset_n == 0)	last_dma_addr_reg	<=	0;
	else if(addressCounter_sload == 1)	
		last_dma_addr_reg	<=	dma_source_reg + dma_modules_reg - 4;
end
always @(posedge master_clk or negedge master_reset_n)
begin
	if(master_reset_n == 0)	dma_current_reg	<=	0;
	else if(addressCounter_sload == 1)	
		dma_current_reg	<=	dma_source_reg;
end

always @(posedge master_clk or negedge master_reset_n)
begin
	if(master_reset_n == 0)
		addressCounter_temp	<=	0;
	else if(addressCounter_sload == 1)
		addressCounter_temp[29:0]	<=	dma_source_reg[31:2];
	else if(addressCounter_incr == 1)
		addressCounter_temp	<=	addressCounter_temp	+	1;
end
endmodule