wuyao_avalon_lcd_controller.v

DE1上avalon总线挂接LCD控制器示例

module wuyao_avalon_lcd_controller(
			// clocks
			//clk_50M,
			tft_clock_25M,
			// avalon master interface
			master_clk,
			master_read,
			master_waitrequest,
			master_readdatavalid,
			master_address,
			master_readdata,
			master_reset_n,
			// avalon slave interface
			slave_reset_n,
			slave_clk,
			slave_chipselect,
			slave_write_n,
			slave_read_n,
			slave_address,
			slave_writedata,
			slave_readdata,				
			// tft LCD interface
			oPCLK,					//pixel clock for lcd
			oHSYNC,					//horizontal sync signal
			oVSYNC,					//vertical sync signal
			oDENA,					//data enable signal
			oPDATA,					//18bit pixel datas
			oSC						//scan direction control signal	
			);
//input			clk_50M;

input			master_clk;
input			master_waitrequest;						
input			master_readdatavalid;
input	[31:0]	master_readdata;
output			master_read;
output	[31:0]	master_address;
input			master_reset_n;

input			slave_reset_n;
input			slave_clk;
input			slave_chipselect;
input			slave_write_n;
input			slave_read_n;
input	[ 1:0]	slave_address;
input	[31:0]	slave_writedata;
output	[31:0]	slave_readdata;

output			oPCLK;
output			oHSYNC;
output			oVSYNC;
output			oDENA;
output	[17:0]	oPDATA;
output			oSC;

//wire			clk_100M;
input			tft_clock_25M;

wire			master_reset_n;
wire			master_read;
wire	[31:0]	master_readdata;
wire			master_waitrequest;
wire			master_readdatavalid;
wire	[31:0]	master_address;

reg				go_bit;
wire			cntr_reg_go_bit;

wire			fifo_rdreq;
wire	[15:0]	fifo_rddata;
wire			fifo_has_room;
wire			fifo_has_data;
wire			fifo_rdempty;
wire			fifo_wrfull;
wire			fifo_wrreq;
wire	[31:0]	fifo_wrdata;
wire	[11:0]	fifo_wrusedw;
wire			fifo_is_ready;
wire			clear_the_fifo;
wire			fifo_read_clk;

wire	[31:0]	dma_source_reg;
wire	[31:0]	dma_modules_reg;
wire	[31:0]	dma_current_reg;
wire	[31:0]	control_reg;

assign	cntr_reg_go_bit	=	control_reg[0];	

always @(posedge master_clk or negedge master_reset_n)
begin
	if(master_reset_n == 0)	go_bit	<=	0;
	else go_bit	<=	cntr_reg_go_bit & fifo_is_ready;
end

control_slave_interface	control_slave_interface_0(
					.slave_reset_n		(slave_reset_n),
					.slave_clk			(slave_clk),
					.slave_chipselect	(slave_chipselect),
					.slave_write_n		(slave_write_n),
					.slave_read_n		(slave_read_n),
					.slave_address		(slave_address),
					.slave_writedata	(slave_writedata),
					.slave_readdata		(slave_readdata),	
					.control_reg		(control_reg),
					.dma_source_reg		(dma_source_reg),
					.dma_modules_reg	(dma_modules_reg),
					.dma_current_reg	(dma_current_reg)
					);
read_master_dma	read_master_dma_0(
					.master_clk			(master_clk),
					.master_reset_n		(cntr_reg_go_bit & master_reset_n),
					.master_read		(master_read),
					.master_address		(master_address),
					.master_waitrequest	(master_waitrequest),
					.master_readdatavalid(master_readdatavalid),
					.master_readdata	(master_readdata),
					.dma_source_reg		(dma_source_reg),
					.dma_modules_reg	(dma_modules_reg),
					.dma_current_reg	(dma_current_reg),
					.dma_writedata		(fifo_wrdata),
					.dma_writefifo		(fifo_wrreq),
					.dma_go_bit			(go_bit),
					.fifo_has_room		(fifo_has_room),
					.clear_the_fifo		(clear_the_fifo)
//for debug use
//					.addressCounter_sload (sload),
//					.addressCounter_incr	(incr)
					);
lcd_fifo_control	lcd_fifo_control(
					.clk				(master_clk),
					.reset_n			(cntr_reg_go_bit),
					.cntr_reg_go_bit	(cntr_reg_go_bit),
					.fifo_wrclk			(master_clk),
					.fifo_wrreq			(fifo_wrreq),
					.fifo_wrdata		(fifo_wrdata),
					.fifo_rdclk			(tft_clock_25M),
					.fifo_rdreq			(fifo_rdreq),
					.fifo_rddata		(fifo_rddata),
					.fifo_wrusedw		(fifo_wrusedw),
					.fifo_has_room		(fifo_has_room),
					.fifo_has_data		(fifo_has_data),
					.fifo_rdempty		(fifo_rdempty),
					.fifo_wrfull		(fifo_wrfull),
					.fifo_is_ready		(fifo_is_ready),
					.clear_the_fifo		(clear_the_fifo),
					.fifo_read_clk		(fifo_read_clk)
					);
tft_timing		tft_timing_0(
					.fifo_rdreq			(fifo_rdreq),
					.fifo_rddata		(fifo_rddata),
					.go_bit				(go_bit),
					.tft_clk			(tft_clock_25M),
					.tft_reset_n		(cntr_reg_go_bit),
					.fifo_has_data		(fifo_has_data),
					.oPCLK				(oPCLK),
					.oHSYNC				(oHSYNC),
					.oVSYNC				(oVSYNC),
					.oDENA				(oDENA),
					.oPDATA				(oPDATA),
					.oSC				(oSC)
					);

endmodule