class.ptf

DE1上avalon总线挂接LCD控制器示例

                        {
                           PORT fifo_rdreq
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT fifo_rddata
                           {
                              width = "16";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT go_bit
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT fifo_has_data
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oPCLK
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oHSYNC
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oVSYNC
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oDENA
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oPDATA
                           {
                              width = "18";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oSC
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     SLAVE tft
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT tft_clk
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "clk";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT tft_reset_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "reset_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "tft_timing";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
                  COMPONENT_BUILDER 
                  {
                     HDL_PARAMETERS 
                     {
                        # generated by CBDocument.getParameterContainer
                        # used only by Component Editor
                        HDL_PARAMETER lines
                        {
                           parameter_name = "LINES";
                           type = "integer";
                           default_value = "480";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER columns
                        {
                           parameter_name = "COLUMNS";
                           type = "integer";
                           default_value = "640";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER thfp
                        {
                           parameter_name = "THFP";
                           type = "integer";
                           default_value = "16";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER thbp
                        {
                           parameter_name = "THBP";
                           type = "integer";
                           default_value = "144";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER twhl
                        {
                           parameter_name = "TWHL";
                           type = "integer";
                           default_value = "96";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER tvfp
                        {
                           parameter_name = "TVFP";
                           type = "integer";
                           default_value = "10";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER tvbp
                        {
                           parameter_name = "TVBP";
                           type = "integer";
                           default_value = "35";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER twvl
                        {
                           parameter_name = "TWVL";
                           type = "integer";
                           default_value = "2";
                           editable = "1";
                           tooltip = "";
                        }
                     }
                  }
               }
            }
         }
         FILE wuyao_avalon_lcd_controller.v
         {
            file_mod = "Mon Jul 09 14:45:54 CST 2007";
            quartus_map_start = "Mon Jul 09 14:46:41 CST 2007";
            quartus_map_finished = "Mon Jul 09 14:46:55 CST 2007";
            #found 1 valid modules
            WRAPPER wuyao_avalon_lcd_controller
            {
               CLASS wuyao_avalon_lcd_controller
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "E:/de2/LCD_Controller/hw2/wuyao_avalon_lcd_controller.v";
                        }
                     }
                     top_module_name = "wuyao_avalon_lcd_controller";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "wuyao_avalon_lcd_controller";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT tft_clock_25M
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_read
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_waitrequest
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_readdatavalid
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_address
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_readdata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oPCLK
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oHSYNC
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";