class.ptf

DE1上avalon总线挂接LCD控制器示例

                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "clk";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                        PORT reset_n
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "reset_n";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "lcd_fifo_control";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
                  COMPONENT_BUILDER 
                  {
                     HDL_PARAMETERS 
                     {
                        # generated by CBDocument.getParameterContainer
                        # used only by Component Editor
                        HDL_PARAMETER uplimit
                        {
                           parameter_name = "UPLIMIT";
                           type = "integer";
                           default_value = "3084";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER downlimit
                        {
                           parameter_name = "DOWNLIMIT";
                           type = "integer";
                           default_value = "512";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER fifo_depth
                        {
                           parameter_name = "FIFO_DEPTH";
                           type = "integer";
                           default_value = "4096";
                           editable = "1";
                           tooltip = "";
                        }
                     }
                  }
               }
            }
         }
         FILE read_master_dma.v
         {
            file_mod = "Sat Jul 07 14:31:07 CST 2007";
            quartus_map_start = "Mon Jul 09 14:39:47 CST 2007";
            quartus_map_finished = "Mon Jul 09 14:39:51 CST 2007";
            #found 1 valid modules
            WRAPPER read_master_dma
            {
               CLASS read_master_dma
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "E:/de2/LCD_Controller/hw2/read_master_dma.v";
                        }
                     }
                     top_module_name = "read_master_dma";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "read_master_dma";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE master
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT master_clk
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "clk";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_reset_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "reset_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT master_read
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_address
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_waitrequest
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_readdatavalid
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT master_readdata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_source_reg
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_modules_reg
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_writedata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_writefifo
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_go_bit
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT fifo_has_room
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT clear_the_fifo
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_current_reg
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT addressCounter_sload
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT addressCounter_incr
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "read_master_dma";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
               }
            }
         }
         FILE tft_timing.v
         {
            file_mod = "Mon Jul 09 14:14:19 CST 2007";
            quartus_map_start = "Mon Jul 09 14:39:51 CST 2007";
            quartus_map_finished = "Mon Jul 09 14:39:55 CST 2007";
            #found 1 valid modules
            WRAPPER tft_timing
            {
               CLASS tft_timing
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "E:/de2/LCD_Controller/hw2/tft_timing.v";
                        }
                     }
                     top_module_name = "tft_timing";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "tft_timing";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING