class.ptf

DE1上avalon总线挂接LCD控制器示例

               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT master_waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT master_readdatavalid
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "readdatavalid";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT master_address
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT master_readdata
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT master_clk
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "clk";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT master_reset_n
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "reset_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "wuyao_avalon_lcd_controller";
         technology = "Wuyao";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "wuyao_avalon_lcd_controller - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
            SBI_avalon_master_0 = "MASTER avalon_master_0/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>wuyao_avalon_lcd_controller 1.0</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2007.07.09.14:49:46";
               }
               TEXT 
               {
                  title = "Class name: wuyao_avalon_lcd_controller";
               }
               TEXT 
               {
                  title = "Class version: 1.0";
               }
               TEXT 
               {
                  title = "Component name: wuyao_avalon_lcd_controller";
               }
               TEXT 
               {
                  title = "Component Group: Wuyao";
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "6.00";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
      }
      SW_FILES 
      {
         FILE 
         {
            filepath = "HAL/inc/wuyao_avalon_lcd_controller.h";
            type = "HAL (HAL/inc/)";
         }
         FILE 
         {
            filepath = "HAL/src/wuyao_avalon_lcd_controller.c";
            type = "HAL (HAL/src/)";
         }
      }
      built_on = "2007.07.09.14:49:46";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE control_slave_interface.v
         {
            file_mod = "Mon Jul 09 14:33:58 CST 2007";
            quartus_map_start = "Mon Jul 09 14:39:20 CST 2007";
            quartus_map_finished = "Mon Jul 09 14:39:37 CST 2007";
            #found 1 valid modules
            WRAPPER control_slave_interface
            {
               CLASS control_slave_interface
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "E:/de2/LCD_Controller/hw2/control_slave_interface.v";
                        }
                     }
                     top_module_name = "control_slave_interface";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "control_slave_interface";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE slave
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT slave_reset_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "reset_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT slave_clk
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "clk";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT slave_chipselect
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "chipselect";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT slave_write_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "write_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT slave_read_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "read_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT slave_address
                           {
                              width = "2";
                              width_expression = "";
                              direction = "input";
                              type = "address";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT slave_writedata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "writedata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT slave_readdata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "readdata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT control_reg
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_source_reg
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_modules_reg
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT dma_current_reg
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "control_slave_interface";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
               }
            }
         }
         FILE lcd_fifo.v
         {
            file_mod = "Mon Jul 09 11:51:58 CST 2007";
            quartus_map_start = "Mon Jul 09 14:39:39 CST 2007";
            quartus_map_finished = "Mon Jul 09 14:39:43 CST 2007";
            #found 1 valid modules
            WRAPPER lcd_fifo
            {
               CLASS lcd_fifo
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES