📄 mcbsp.h.bak
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receive data.Applicable to 8-bit data only. */
MCBSP_XCR_XFIG_YES, /* Transmit frame ignore(XFIG)
MCBSP_XCR_XFIG_NO - Unexpected transmit frame
synchronization pulses restart the transfer.
MCBSP_XCR_XFIG_YES - Unexpected transmit frame
synchronization pulses are ignored. */
MCBSP_XCR_XDATDLY_0BIT, /* Transmit data delay(XDATDLY)
MCBSP_XCR_XDATDLY_0BIT - 0 bit data delay
MCBSP_XCR_XDATDLY_1BIT - 1 bit data delay
MCBSP_XCR_XDATDLY_2BIT - 2 bit data delay */
MCBSP_XCR_XFRLEN1_OF(1), /* Transmit frame length in phase 1(XFRLEN1)
000 0000b: 1 word per phase
000 0001b: 2 words per phase
. . . . . . . . . . . .
111 1111b: 128 words per phase */
MCBSP_XCR_XWDLEN1_16BIT, /* Transmit element length in phase 1(XWDLEN1)
MCBSP_XCR_XWDLEN1_8BIT - 8 bits
MCBSP_XCR_XWDLEN1_12BIT - 12 bits
MCBSP_XCR_XWDLEN1_16BIT - 16 bits
MCBSP_XCR_XWDLEN1_20BIT - 20 bits
MCBSP_XCR_XWDLEN1_24BIT - 24 bits
MCBSP_XCR_XWDLEN1_32BIT - 32 bits */
MCBSP_XCR_XWDREVRS_DISABLE /* Transmit 32-bit bit reversal feature
MCBSP_XCR_XWDREVRS_DISABLE - 32-bit reversal
disabled.
MCBSP_XCR_XWDREVRS_ENABLE - 32-bit reversal
enabled. 32-bit data is transmitted LSB first.
XWDLEN should be set for 32-bit operation.
XCOMPAND should be set to 01b; else operation
is undefined. */
),
/*serial port sample rate generator register(SRGR) */
MCBSP_SRGR_RMK(
MCBSP_SRGR_GSYNC_FREE,/* Sample rate generator clock synchronization(GSYNC).
MCBSP_SRGR_GSYNC_FREE - The sample rate generator
clock CLKG) is free running.
MCBSP_SRGR_GSYNC_SYNC - (CLKG) is running but is
resynchronized, and the frame sync signal
(FSG)is generated only after the receive
frame synchronization signal(FSR)is detected.
Also,the frame period (FPER) is a don抰 care
because the period is dictated by the external
frame sync pulse. */
MCBSP_SRGR_CLKSP_RISING,/* CLKS polarity clock edge select(CLKSP)
MCBSP_SRGR_CLKSP_RISING - The rising edge of CLKS
generates CLKG and FSG.
MCBSP_SRGR_CLKSP_FALLING - The falling edge of CLKS
generates CLKG and FSG. */
MCBSP_SRGR_CLKSM_INTERNAL,/* MCBSP sample rate generator clock mode(CLKSM)
MCBSP_SRGR_CLKSM_CLKS - The sample rate generator
clock is derived from CLKS.
MCBSP_SRGR_CLKSM_INTERNAL - (Default value) The
sample rate generator clock is derived from
the internal clock source. */
MCBSP_SRGR_FSGM_DXR2XSR,/*Sample rate generator transmit frame synchronization
mode.(FSGM)
MCBSP_SRGR_FSGM_DXR2XSR - The transmit frame sync
signal (FSX) is generated on every DXR to XSR
copy.
MCBSP_SRGR_FSGM_FSG - The transmit frame sync
signal is driven by the sample rate generator
frame sync signal, FSG. */
MCBSP_SRGR_FPER_OF(63),/* Frame period(FPER)
Valid values: 0 to 4095 */
MCBSP_SRGR_FWID_OF(31),/* Frame width(FWID)
Valid values: 0 to 255 */
MCBSP_SRGR_CLKGDV_OF(15)/* Sample rate generator clock divider(CLKGDV)
Valid values: 0 to 255 */
),
MCBSP_MCR_DEFAULT, /* Using default value of MCR register */
MCBSP_RCER_DEFAULT,/* Using default value of RCER register */
MCBSP_XCER_DEFAULT,/* Using default value of XCER register */
/* serial port pin control register(PCR) */
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_SP, /* Transmitter in general-purpose I/O mode - only when
XRST = 0 in SPCR - (XIOEN)
MCBSP_PCR_XIOEN_SP - CLKS pin is not a general
purpose input. DX pin is not a general purpose
output.FSX and CLKX are not general-purpose I/Os.
MCBSP_PCR_XIOEN_GPIO - CLKS pin is a general-purpose
input. DX pin is a general-purpose output.
FSX and CLKX are general-purpose I/Os. These
serial port pins do not perform serial port
operation. */
MCBSP_PCR_RIOEN_SP, /* Receiver in general-purpose I/O mode - only when
RRST = 0 in SPCR -(RIOEN)
MCBSP_PCR_RIOEN_SP - DR and CLKS pins are not
general-purpose inputs. FSR and CLKR are not
general-purpose I/Os and perform serial port
operation.
MCBSP_PCR_RIOEN_GPIO - DR and CLKS pins are
general-purpose inputs. FSR and CLKR are
general-purpose I/Os. These serial port pins do
not perform serial port operation. */
MCBSP_PCR_FSXM_EXTERNAL, /* Transmit frame synchronization mode(FSXM)
MCBSP_PCR_FSXM_EXTERNAL - Frame synchronization
signal is provided by an external source. FSX
is an input pin.
MCBSP_PCR_FSXM_INTERNAL - Frame synchronization
generation is determined by the sample rate
generator frame synchronization mode bit FSGM
in the SRGR. */
MCBSP_PCR_FSRM_EXTERNAL, /* Receive frame synchronization mode (FSRM)
MCBSP_PCR_FSRM_EXTERNAL - Frame synchronization
signals are generated by an external device.
FSR is an input pin.
MCBSP_PCR_FSRM_INTERNAL - Frame synchronization
signals are generated internally by the sample
rate generator. FSR is an output pin except
when GSYNC = 1 in SRGR. */
MCBSP_PCR_CLKXM_INPUT, /* Transmitter clock mode (CLKXM)
MCBSP_PCR_CLKXM_INPUT - Transmitter clock is
driven by an external clock with CLKX as an
input pin.
MCBSP_PCR_CLKXM_OUTPUT - CLKX is an output pin
and is driven by the internal sample rate
generator.
During SPI mode :
MCBSP_PCR_CLKXM_INPUT - McBSP is a slave and
(CLKX) is driven by the SPI master in the
system. CLKR is internally driven by CLKX.
MCBSP_PCR_CLKXM_OUTPUT - McBSP is a master and
generates the transmitter clock (CLKX) to
drive its receiver clock (CLKR) and the shift
clock of the SPI-compliant slaves in the
system. */
MCBSP_PCR_CLKRM_INPUT, /* Receiver clock mode (CLKRM)
Case 1: Digital loopback mode not set in SPCR
MCBSP_PCR_CLKRM_INPUT - Receive clock (CLKR) is
an input driven by an external clock.
MCBSP_PCR_CLKRM_OUTPUT - CLKR is an output pin
and is driven by the sample rate generator.
Case 2: Digital loopback mode set in SPCR
MCBSP_PCR_CLKRM_INPUT - Receive clock is driven
by the transmit clock (CLKX), which is based
on the CLKXM bit in PCR. CLKR is in high
impedance.
MCBSP_PCR_CLKRM_INPUT - CLKR is an output pin and
is driven by the transmit clock. The transmit
clock is derived from CLKXM bit in the PCR.*/
MCBSP_PCR_CLKSSTAT_0, /* CLKS pin status(CLKSSTAT)
MCBSP_PCR_CLKSSTAT_0
MCBSP_PCR_CLKSSTAT_1 */
MCBSP_PCR_DXSTAT_0, /* DX pin status(DXSTAT)
MCBSP_PCR_DXSTAT_0
MCBSP_PCR_DXSTAT_1 */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* Transmit frame synchronization polarity(FSXP)
MCBSP_PCR_FSXP_ACTIVEHIGH - Frame synchronization
pulse FSX is active high
MCBSP_PCR_FSXP_ACTIVELOW - Frame synchronization
pulse FSX is active low */
MCBSP_PCR_FSRP_ACTIVEHIGH, /* Receive frame synchronization polarity(FSRP)
MCBSP_PCR_FSRP_ACTIVEHIGH - Frame synchronization
pulse FSR is active high
MCBSP_PCR_FSRP_ACTIVELOW - Frame synchronization
pulse FSR is active low */
MCBSP_PCR_CLKXP_RISING, /* Transmit clock polarity(CLKXP)
MCBSP_PCR_CLKXP_RISING - Transmit data driven on
rising edge of CLKX
MCBSP_PCR_CLKXP_FALLING - Transmit data driven on
falling edge of CLKX */
MCBSP_PCR_CLKRP_FALLING /* Receive clock polarity(CLKRP)
MCBSP_PCR_CLKRP_FALLING - Receive data sampled on
falling edge of CLKR
MCBSP_PCR_CLKRP_RISING - Receive data sampled on
rising edge of CLKR */
)
};
static MCBSP_Config ConfigMcbsp1 = {
0x02000000, //SPCR
0x00040140, //RCR
0x00040140, //XCR
MCBSP_SRGR_DEFAULT,
MCBSP_MCR_DEFAULT, /* Using default value of MCR register */
MCBSP_RCER_DEFAULT,/* Using default value of RCER register */
MCBSP_XCER_DEFAULT,/* Using default value of XCER register */
0x00000001
};
//==============================================
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