bbu_nand.s

NAND DRV

; 
; INTEL CONFIDENTIAL
; Copyright 2006 Intel Corporation All Rights Reserved.
;
; The source code contained or described herein and all documents
; related to the source code (Material) are owned by Intel Corporation
; or its suppliers or licensors.  Title to the Material remains with
; Intel Corporation or its suppliers and licensors. The Material contains
; trade secrets and proprietary and confidential information of Intel
; or its suppliers and licensors. The Material is protected by worldwide
; copyright and trade secret laws and treaty provisions. No part of the
; Material may be used, copied, reproduced, modified, published, uploaded,
; posted, transmitted, distributed, or disclosed in any way without Intel's
; prior express written permission.
;
; No license under any patent, copyright, trade secret or other intellectual
; property right is granted to or conferred upon you by disclosure or
; delivery of the Materials, either expressly, by implication, inducement,
; estoppel or otherwise. Any license under such intellectual property rights
; must be express and approved by Intel in writing.
;
;
;*******************************************************************************
;
;                                  bbu_NAND.s
;       BBU subroutines for communicating with devices connected to the
;       Data Flash Controller.
;
;
        GLOBAL  BBU_DFC_Init    ; Sets up the Data Flash Controller for use
        GLOBAL  BBU_NAND_read   ; Read a 512 byte page from NAND flash
        GLOBAL  BBU_NAND_erase  ; Erase a 512 byte page from NAND flash
        GLOBAL  BBU_NAND_ID     ; Returns the NAND flash ID
        GLOBAL  BBU_NAND_unlock ; Unlock the NAND flash (for writing)

        EXTERN  BBU_tickWait    ; Delay for x clock ticks (1 tick = 0.271267 uS)
        EXTERN  xlli_Smem_init
;
;*******************************************************************************
;       DEFINITIONS USED IN THIS FILE
;*******************************************************************************
;
BBU_DFC_Physical_Base   EQU     0x43100000      ; Physical base address of the Data Flash Controller
;
;       Offsets
;
BBU_NDCR_offset         EQU     0x00    ; Offset to Data Flash Control Register
BBU_NDTR0CS0_offset     EQU     0x04    ; Offest to Data Control Timing Paramter 0
BBU_NDTR1CS0_offset     EQU     0x0C    ; Offest to Data Control Timing Paramter 1
BBU_NDSR_offset         EQU     0x14    ; Offset to Data Control Status Register
BBU_NDDB_offset         EQU     0x40    ; Offset to Data Controller data buffer (input and output)
BBU_NDCB0_offset        EQU     0x48    ; Offset to Data Controller Command Buffer 0
;
;       Bit defs
;
BBU_NDSR_WRCMDREQ       EQU     0x00000001      ; Write command request bit
BBU_NDSR_RDDREQ         EQU     0x00000002      ; Read Data Request
BBU_NDSR_CS0_CMDD       EQU     0x00000100      ; ND_nCS0 command is done

BBU_NDCR_ND_RUN         EQU     0x10000000      ; NAND Controller RUN mode bit
;
;       BBU default register values
;
BBU_NDCR_value          EQU     0xCC071FFF      ;
BBU_NDTR0CS0_value      EQU     0x00081414      ; Boot up value is 0x00111D1D
BBU_NDTR1CS0_value      EQU     0x06180061      ; Boot up value is 0x04D400D2
;BBU_NDTR0CS0_value      EQU     0x00111D1D      ; Boot up value is 0x00111D1D
;BBU_NDTR1CS0_value      EQU     0x04D400D2      ; Boot up value is 0x04D400D2
BBU_NDSR_value          EQU     0x00000FFF      ; Clears status register sticky bits


        AREA  |text|,CODE,READONLY
;
;*******************************************************************************
;
;       ****************
;       *              * 
;       * BBU_DFC_Init *       Set up Data Flash Controller for use
;       *              *
;       ****************
;
;       PARAMETERS
;
;               No parameters 
;
BBU_DFC_Init    FUNCTION

        stmfd   sp!,    {r0-r2, lr}     ; Save r0-r2, and link register on the stack

        bl      xlli_Smem_init

        ldr     r0,     =0x40E10200     ; load MFPR base address + 200 into r0
        ldr     r1,     =0x00001901     ; Drive strength and Alternate Fuction value
        str     r1,     [r0, #0x24]     ; Load MFPR register for ND_CS0
        str     r1,     [r0, #0x28]     ; Load MFPR register for ND_CS1
        str     r1,     [r0, #0x2C]     ; Load MFPR register for ND_nWE
        str     r1,     [r0, #0x30]     ; Load MFPR register for ND_nRE
        ldr     r1,     =0x00001900     ; Drive strength and Alternate Fuction value
        str     r1,     [r0, #0x04]     ; Load MFPR register for ND_CLE
        ldr     r1,     =0x0000D881     ; Drive strength and Alternate Fuction value
        str     r1,     [r0, #0x1C]     ; Load MFPR register for ND_ALE

        ldr     r0,     =BBU_DFC_Physical_Base  ; Base Address of NAND controller
        mov     r1,     #0                      ; Clear out a work register
        str     r1,     [r0, #BBU_NDCR_offset]  ; Write control register
        ldr     r2,     =BBU_NDTR0CS0_value             ; Set up value for timing register 0
        str     r2,     [r0, #BBU_NDTR0CS0_offset]      ; Write this value out to the controller
        ldr     r2,     =BBU_NDTR1CS0_value             ; Set up value for timing register 1
        str     r2,     [r0, #BBU_NDTR1CS0_offset]      ; Write this value out to the controller
        ldr     r1,     =BBU_NDSR_value                 ; Setup to clear status register sticky bits
        str     r1,     [r0, #BBU_NDSR_offset]  ; Write this value to the controller
        ldr     r1,     =BBU_NDCR_value         ; Setup for Data Flash Controller Register
        str     r1,     [r0, #BBU_NDCR_offset]  ; Write this value to the control register
;
;       Do some dummy reads (intent is to make sure the buffer is empty)
;
        mov     r2,     #0x40                   ; Set up a loop count
10      ldr     r1,     [r0, #BBU_NDDB_offset]  ; Dummy read
        subs    r2,     r2,     #1              ; Decrement loop count
        bne     %B10                            ; Loop until counter is zero
;
;       Return to caller with controller ready to accept a command
;
        ldmfd   sp!,    {r0-r2, pc}     ; Restore r0-r2, and return to caller
        ENDFUNC
;
;*******************************************************************************
;
;       *****************
;       *               * 
;       * BBU_NAND_read *        Read data from the NAND flash
;       *               *      (reads a single page - 512 bytes)
;       *****************
;
;       INPUT:
;
;               r0 = NAND source address (preserved)
;               r1 = Destination address (preserved)
;
BBU_NAND_read   FUNCTION

        stmfd   sp!,    {r0-r3, lr}     ; Save r0-r3, and link register on the stack
;
;       Program controller for the read
;
        ldr     r3,     =BBU_DFC_Physical_Base  ; Base Address of NAND controller
        ldr     r2,     [r3, #BBU_NDDB_offset]  ; Read the data buffer (dummy read)
        ldr     r2,     [r3, #BBU_NDDB_offset]  ; Read the data buffer (dummy read)
        ldr     r2,     [r3, #BBU_NDDB_offset]  ; Read the data buffer (dummy read)
        ldr     r2,     [r3, #BBU_NDDB_offset]  ; Read the data buffer (dummy read)
;
;       Set the controller into run mode
;
        ldr     r2,     [r3, #BBU_NDCR_offset]  ; Fetch the contents of the Control register
        orr     r2,     r2,     #BBU_NDCR_ND_RUN; Set the ND_RUN bit 
        str     r2,     [r3, #BBU_NDCR_offset]  ; Write control register back
;
;       Write the command to the command buffers
;
        mov     r2,     #0x40000                ; Read command
        str     r2,     [r3, #BBU_NDCB0_offset] ; Write to register
        str     r0,     [r3, #BBU_NDCB0_offset] ; Write addrs cycle 1:4
        mov     r2,     #0x0                    ; Specify 1 page to be transfered
        str     r2,     [r3, #BBU_NDCB0_offset] ; Write address cycle 5 and page count
;
;       Wait for command to finish
;
20      ldr     r0,     [r3, #BBU_NDSR_offset]  ; Read NDSR register
        ands    r0,     r0,     #BBU_NDSR_RDDREQ; Test RDDREQ bit (ready to read a page?)
        beq     %B20                            ; Loop until data is ready
        str     r0,     [r3, #BBU_NDSR_offset]  ; Clear the sticky bit
;
;       Copy data from NAND controler to destination address
;
        ldr     r2,     =0x80                   ; A page is 512 bytes (0x80 32-bit words)
30      ldr     r0,     [r3, #BBU_NDDB_offset]  ; Read the data buffer
        str     r0,     [r1],   #4              ; Write to destination address and increment
        subs    r2,     r2,     #1              ; Decrement word count
        bne     %B30                            ; Keep looping until the page is transfered
;
;       Read any data form the spare area (and toss it)
;
        ldr     r0,     [r3, #BBU_NDDB_offset]  ; Read spare area (dummy read)
        ldr     r0,     [r3, #BBU_NDDB_offset]  ; Read spare area (dummy read)
        ldr     r0,     [r3, #BBU_NDDB_offset]  ; Read spare area (dummy read)
        ldr     r0,     [r3, #BBU_NDDB_offset]  ; Read spare area (dummy read)