📄 start91460.asm
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;
; PON : Power-on control
; 0 : disabled
; 1 : power-on sequence started
;
; RFC2 RFC1 RFC0 : Refresh Count
; 0 0 0 : 256
; 0 0 1 : 512
; 0 1 0 : 1024
; 0 1 1 : 2048
; 1 0 0 : 4096
; 1 0 1 : 8192
; 1 1 0 : Setting disabled
; 1 1 1 : Refresh disabled
;
; BRST : Burst refresh control
; 0 : Decentralised refresh
; 1 : burst refresh
;
; RFINT[5-0] : auto refresh interval
;
; RRLD : Refresh counter Activation Control
; 0 : Disabled,
; 1 : Autorefresh performed once, then value of RFINT reloaded
;
; SELF : Self refresh control
; 0 : auto refresh or power down
; 1 : Transitions to self-refresch mode
;
; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the
; above setting. Otherwise the settings are not correct set.
;
;=========================================================================================
; 4.8.7 Terminal and Timing Control Register (only EXTBUS == ON)
;=========================================================================================
;
#set TIMECONTR B'00000000 ; <<< set TCR register, TCR
; ||||||||
; ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1)
; |||||||___ RDW1 bit
; ||||||____ OHT0 bit, set output hold delay (OHT1,0)
; |||||_____ OHT1 bit
; ||||______ reserved, always write 0
; |||_______ PCLR bit, prefetch buffer clear
; ||________ PSUS bit, prefetch suspend
; |_________ BREN bit, BRQ input enable
;
; This register controls the general functions of the external bus interface controller
; such as the common-pin function setting and timing control.
;
; Bit description:
;
; RDW1 RDW0 : Wait cycle reduction
; 0 0 : Normal Wait (AWR0 - 7 setting)
; 0 1 : 1/2 of AWR0 - 7 setting value
; 1 0 : 1/4 of AWR0 - 7 setting value
; 1 1 : 1/8 of AWR0 - 7 setting value
;
; OHT1 OHT0 : Output hold selection bit
; 0 0 : Output performed at falling edge of SYSCLK/MCLK
; 0 1 : Output performed about 3ns after falling edge of SYSCLK/MCLK
; 1 0 : Output performed about 4ns after falling edge of SYSCLK/MCLK
; 1 1 : Output performed about 5ns after falling edge of SYSCLK/MCLK
;
; PCLR : Prefetch buffer all clear
; 0 : normal state
; 1 : Prefetch buffer cleared
;
; PSUS : prefetch suspension bit
; 0 : Prefetch enabled
; 1 : Prefetch disabled
;
; BREN : BRQ input enable
; 0 : disabled,
; 1 : enabled, Bus sharing of BRQ/BGRNTX performed
;
; Note: This function is used to prevent an excessive access cycle wait while operating
; at a low-speed clock (such as while base clock operating at low speed or
; high frequency division rate for external bus clock).
;
;=========================================================================================
; 4.8.8 Enable/Disable I-CACHE (only EXTBUS == ON)
;=========================================================================================
;
#set C1024 1 ; CACHE Size: 1024 BYTE
#set C2048 2 ; CACHE Size: 2048 BYTE
#set C4096 3 ; CACHE Size: 4096 BYTE
;
;
#set CACHE OFF ; <<< Select use of cache
#set CACHE_SIZE C4096 ; <<< Select size of cache, ISIZE
;
; It is possible to use cache functionality on the I-Bus on several devices. Please
; check the corresponidng data sheet if this feature is available on a certain device
; and for the size of the cache. This is the general cache configuration. It is possible
; to configure for each CS area, if the cache should be used.
;
; Note: This feature is not supported by every device. Please check the data sheet. The
; feature is for example supported by MB91461R, MB91469G.
;
;=========================================================================================
; 4.8.9 Enable CACHE for chipselect (only EXTBUS == ON)
;=========================================================================================
;
#set CHEENA B'11111111 ; <<< en-/disable cache, CHER
; ||||||||
; ||||||||__ CHE0 bit, CS0 area
; |||||||___ CHE1 bit, CS1 area
; ||||||____ CHE2 bit, CS2 area
; |||||_____ CHE3 bit, CS3 area
; ||||______ CHE4 bit, CS4 area
; |||_______ CHE5 bit, CS5 area
; ||________ CHE6 bit, CS6 area
; |_________ CHE7 bit, CS7 area
;
; Additional to the general cache enable setting, select which CS area should be used
; with cache functionality.
;
; Note: Not all Chipselects are supported by the different devices. Please check the
; data sheet.
;
; Note: This feature is not supported by every device. Please check the data sheet. The
; Feature is supported by MB91461R, MB91469G.
;
;=========================================================================================
; 4.8.10 Select External bus mode (Data lines) (only EXTBUS == ON)
;=========================================================================================
;
#set PFUNC0 B'11111111 ;<<< Data lines or GIO, PFR00
; ||||||||
; ||||||||__ D24 / P00_0
; |||||||___ D25 / P00_1
; ||||||____ D26 / P00_2
; |||||_____ D27 / P00_3
; ||||______ D28 / P00_4
; |||_______ D29 / P00_5
; ||________ D30 / P00_6
; |_________ D31 / P00_7
;
#set PFUNC1 B'11111111 ;<<< Data lines or GIO, PFR01
; ||||||||
; ||||||||__ D16 / P01_0
; |||||||___ D17 / P01_1
; ||||||____ D18 / P01_2
; |||||_____ D19 / P01_3
; ||||______ D20 / P01_4
; |||_______ D21 / P01_5
; ||________ D22 / P01_6
; |_________ D23 / P01_7
;
#set PFUNC2 B'11111111 ;<<< Data lines or GIO, PFR02
; ||||||||
; ||||||||__ D8 / P02_0
; |||||||___ D9 / P02_1
; ||||||____ D10 / P02_2
; |||||_____ D11 / P02_3
; ||||______ D12 / P02_4
; |||_______ D13 / P02_5
; ||________ D14 / P02_6
; |_________ D15 / P02_7
;
#set PFUNC3 B'11111111 ;<<< Data lines or GIO, PFR03
; ||||||||
; ||||||||__ D0 / P03_0
; |||||||___ D1 / P03_1
; ||||||____ D2 / P03_2
; |||||_____ D3 / P03_3
; ||||______ D4 / P03_4
; |||_______ D5 / P03_5
; ||________ D6 / P03_6
; |_________ D7 / P03_7
;
; Select if the ports are set to
; 1 : External bus mode, I/O for data lines or
; 0 : General I/O port (GIO)
;
; Note: Not all data-lines are supported by the different devices. Please check the data
; sheet.
;
;=========================================================================================
; 4.8.11 Select External bus mode (Address lines) (only EXTBUS == ON)
;=========================================================================================
;
#set PFUNC4 B'11111111 ;<<< Address lines or GIO, PFR04
; ||||||||
; ||||||||__ A24 / P04_0
; |||||||___ A25 / P04_1
; ||||||____ A26 / P04_2
; |||||_____ A27 / P04_3
; ||||______ A28 / P04_4
; |||_______ A29 / P04_5
; ||________ A30 / P04_6
; |_________ A31 / P04_7
;
#set PFUNC5 B'11111111 ;<<< Address lines or GIO, PFR05
; ||||||||
; ||||||||__ A16 / P05_0
; |||||||___ A17 / P05_1
; ||||||____ A18 / P05_2
; |||||_____ A19 / P05_3
; ||||______ A20 / P05_4
; |||_______ A21 / P05_5
; ||________ A22 / P05_6
; |_________ A23 / P05_7
;
#set PFUNC6 B'11111111 ;<<< Address lines or GIO, PFR06
; ||||||||
; ||||||||__ A8 / P06_0
; |||||||___ A9 / P06_1
; ||||||____ A10 / P06_2
; |||||_____ A11 / P06_3
; ||||______ A12 / P06_4
; |||_______ A13 / P06_5
; ||________ A14 / P06_6
; |_________ A15 / P06_7
;
#set PFUNC7 B'11111111 ;<<< Address lines or GIO, PFR07
; ||||||||
; ||||||||__ A0 / P07_0
; |||||||___ A1 / P07_1
; ||||||____ A2 / P07_2
; |||||_____ A3 / P07_3
; ||||______ A4 / P07_4
; |||_______ A5 / P07_5
; ||________ A6 / P07_6
; |_________ A7 / P07_7
;
; Select if the ports are set to
; 1 : External bus mode, I/O for address lines or
; 0 : General I/O port (GIO)
;
; Note: Not all address-lines are supported by the different devices. Please check the
; data sheet.
;
;=========================================================================================
; 4.8.12 Select External bus mode (Control signals) (only EXTBUS == ON)
;=========================================================================================
;
#set PFUNC8 B'11111111 ;<<< Control signals or GIO, PFR08
; ||||||||
; ||||||||__ WRX0 / P08_0
; |||||||___ WRX1 / P08_1
; ||||||____ WRX2 / P08_2
; |||||_____ WRX3 / P08_3
; ||||______ RDX / P08_4
; |||_______ BGRNTX / P08_5
; ||________ BRQ / P08_6
; |_________ RDY / P08_7
;
#set PFUNC9 B'11111111 ;<<< Control signals or GIO, PFR09
; ||||||||
; ||||||||__ CSX0 / P09_0
; |||||||___ CSX1 / P09_1
; ||||||____ CSX2 / P09_2
; |||||_____ CSX3 / P09_3
; ||||______ CSX4 / P09_4
; |||_______ CSX5 / P09_5
; ||________ CSX6 / P09_6
; |_________ CSX7 / P09_7
;
#set PFUNC10 B'01011111 ;<<< Control signals or GIO, PFR10
; ||||||||
; ||||||||__ SYSCLK or !SYSCLK / P10_0
; |||||||___ ASX / P10_1
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