📄 start91460.asm
字号:
; 0 1 : 16-bit (HALF-WORD access)
; 1 0 : 32-bit (WORD access)
; 1 1 : Reserved
;
; ASZ3 ASZ2 ASZ1 ASZ0 : Select memory size of each chipselect
; 0 0 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[31:16] bits)
; 0 0 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits)
; 0 0 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits)
; 0 0 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits)
; 0 1 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[31:20] bits)
; 0 1 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[31:21] bits)
; 0 1 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[31:22] bits)
; 0 1 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[31:23] bits)
; 1 0 0 0 : 16 Mbyte (0x100.0000 bytes; use ASR A[31:24] bits)
; 1 0 0 1 : 32 Mbyte (0x200.0000 bytes; use ASR A[31:25] bits)
; 1 0 1 0 : 64 Mbyte (0x400.0000 bytes; use ASR A[31:26] bits)
; 1 0 1 1 : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits)
; 1 1 0 0 : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits)
; 1 1 0 1 : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits)
; 1 1 1 0 : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits)
; 1 1 1 1 : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit)
;
;=========================================================================================
; 4.8.4 Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON)
;=========================================================================================
;
; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)
;
#set WAITREG0 B'0000000000000000 ; <<< CS0 Waitstates, AWR0
#set WAITREG1 B'0000000000000000 ; <<< CS1 Waitstates, AWR1
#set WAITREG2 B'0000000000000000 ; <<< CS2 Waitstates, AWR2
#set WAITREG3 B'0000000000000000 ; <<< CS3 Waitstates, AWR3
#set WAITREG4 B'0000000000000000 ; <<< CS4 Waitstates, AWR4
#set WAITREG5 B'0000000000000000 ; <<< CS5 Waitstates, AWR5
; ||||||||||||||||
; ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle
; |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle
; ||||||||||||||____ W02 bit, Address -> CSX Delay selection
; |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing
; ||||||||||||______ W04 bit, W04/W05 Write recovery cycle
; |||||||||||_______ W05 bit
; ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle
; |||||||||_________ W07 bit selection
; ||||||||__________ W08 bit, W08-W11 Intra-page access cycle
; |||||||___________ W09 bit select (0-15 cycles)
; ||||||____________ W10 bit
; |||||_____________ W11 bit
; ||||______________ W12 bit, W12-W15 First access wait cycle
; |||_______________ W13 bit select (0-15 cycles)
; ||________________ W14 bit
; |_________________ W15 bit
;
;
; SDRAM and FRAM bus interface (ACRx_Type = 100x)
;
#set WAITREG6 B'0000000000000000 ; <<< CS6 Waitstates, AWR6
#set WAITREG7 B'0000000000000000 ; <<< CS7 Waitstates, AWR7
; ||||||||||||||||
; ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles
; |||||||||||||||___ W01 bit
; ||||||||||||||____ W02 bit, W2-W3 RAS active Time
; |||||||||||||_____ W03 bit
; ||||||||||||______ W04 bit, W4-W5 Write recovery cycle
; |||||||||||_______ W05 bit
; ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle
; |||||||||_________ W07 bit
; ||||||||__________ W08 bit, W8-W10 CAS latency
; |||||||___________ W09 bit
; ||||||____________ W10 bit
; |||||_____________ W11 bit, reserved
; ||||______________ W12 bit, W12-W16 RAS-CAS delay
; |||_______________ W13 bit
; ||________________ W14 bit
; |_________________ W15 bit, reserved
;
;
; The bit meaning depends on the configured bus interface type. The bus interface can be
; configured for different memory types. Depending on the memory type, the wait register
; bits have a differnt meaning. CS0-5 should be configurable as ordinary bus interface
; (w/o SDRAM and FRAM) and CS6-7 should be configurable as SDRAM and FRAM. It is also
; possible and for some devices neccessary to configure other two chip selects as SDRAM
; or FRAM interface. In such a case be aware of the bit meanings.
;
;
; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)
; --------------------------------------------------------------
;
; Bit description:
;
; W00 : RDY/WRX -> CSX hold extension cycle
; 0 : 0 cycle
; 1 : 1 cycle
;
; W01 : CSX -> RDX/WRX setup extention cycle
; 0 : 0 cycle
; 1 : 1 cycle
;
; W02 : Address -> CSX Delay selection
; 0 : no delay selected
; 1 : delay selected
;
; W03 : WR0X to WR3X/WRX outout timing selection
; 0 : MCLK synchronous write output enable (ASX=L)
; 1 : Asynchronous write strobe output (norma operation)
;
; W05 W04 : select Write recovery cycle
; 0 0 : 0 cycle
; 0 1 : 1 cycle
; 1 0 : 2 cycles
; 1 1 : 3 cycles
;
; W07 W06 : Read -> Write idle cycle selection
; 0 0 : 0 cycle
; 0 1 : 1 cycle
; 1 0 : 2 cycles
; 1 1 : 3 cycles
;
; W11 W10 W09 W08 : Intra-page access cycle select (0-15 cycles)
; 0 0 0 0 : 0 Wait state
; 0 0 0 1 : 1 Auto-wait cycle
; 0 0 1 0 : 2 Auto-wait cycle
; ....
; 1 1 1 1 : 15 Auto wait cycles
;
; W15 W14 W13 W12 : First access wait cycle can be set (0-15 cycles)
; 0 0 0 0 : 0 Wait state
; 0 0 0 1 : 1 Auto-wait cycle
; 0 0 1 0 : 2 Auto-wait cycle
; ....
; 1 1 1 1 : 15 Auto wait cycles
;
;
;
; SDRAM and FRAM bus interface (ACRx_Type = 100x)
; -----------------------------------------------
;
; Bit description:
;
; W01 W00 : RAS precharge cycles.
; 0 0 : 1 cycle
; 0 1 : 2 cycles
; 1 0 : 5 cycles
; 1 1 : 6 cycles
;
; W03 W02 : RAS active Time
; 0 0 : 1 cycle
; 0 1 : 2 cycles
; 1 0 : 5 cycles
; 1 1 : 6 cycles
;
; W05 W04 : set Write recovery cycle (1 - 4 cycles)
; 0 0 : Prohibited
; 0 1 : 2 cycles
; 1 0 : 3 cycles
; 1 1 : 4 cycles
;
; W07 W06 : set Read -> Write idle Cycle (1 - 4 cycles)
; 0 0 : 1 cycle
; 0 1 : 2 cycles
; 1 0 : 3 cycles
; 1 1 : 4 cycles
;
; W10 W09 W08 : set CAS latency (1 - 8 cycles)
; 0 0 0 : 1 cycle
; 0 0 1 : 2 cycle
; ...
; 1 1 1 : 8 cycle
;
; W11 : RESERVED, ALWAYS WRITE 0 !
;
; W14 W13 W12 : set RAS-CAS delay (1 - 8 cycles)
; 0 0 0 : 1 cycle
; 0 0 1 : 2 cycle
; ...
; 1 1 1 : 8 cycle
;
; W15 : RESERVED, ALWAYS WRITE 0 !
;
; The bit meaning depends on the configured bus interface type
;
;=========================================================================================
; 4.8.5 Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM)
;=========================================================================================
;
#set MEMCON B'00000111 ; <<< set special SDRAM register, MCRA
; ||||||||
; ||||||||__ ABS0 bit, set max. active banks (ABS1,0)
; |||||||___ ABS1 bit
; ||||||____ BANK bit, set number of banks connected to CS
; |||||_____ WBST bit, Write burst enable/disable
; ||||______ PSZ0 bit, Set page size (PSZ2-0)
; |||_______ PSZ1 bit
; ||________ PSZ2 bit
; |_________ reserved, always write 0
;
; When connecting SDRAM/FCRAM TYP3-0=1000 in ACRx register the following register must
; be setup.
;
; Bit description:
;
; ABS1 ABS0 : Set maximum number of bank, active at same time
; 0 0 : 1 bank
; 0 1 : 2 banks
; 1 0 : 3 banks
; 1 1 : 4 banks
;
; BANK : Set number of connected SDRAM banks
; 0 : 2 banks
; 1 : 4 banks
;
; WBST : Write burst enable
; 0 : Single Write
; 1 : Busrt Write
;
; PSZ2 PSZ1 PS0 : Select page size of connected memory
; 0 0 0 : 8-bit column address = A0 to A7
; 0 0 1 : 9-bit column address = A0 to A8
; 0 1 0 : 10-bit column address = A0 to A9
; 0 1 1 : 11-bit column address = A0 to A9, A11
; 1 X X : setting disabled
;
;
;=========================================================================================
; 4.8.6 Referesh Control Register RCR (only EXTBUS == ON and SDRAM)
;=========================================================================================
;
#set REFRESH B'1110001001000111 ; <<< set Refresh Control Register, RCR
; ||||||||||||||||
; ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0)
; |||||||||||||||___ TRC1 bit
; ||||||||||||||____ TRC2 bit
; |||||||||||||_____ PON bit, set power-on control
; ||||||||||||______ RFC0 bit, set refresh count (RFC2-0)
; |||||||||||_______ RFC1 bit
; ||||||||||________ RFC2 bit
; |||||||||_________ BRST bit, set burst refresh control
; ||||||||__________ RFINT0 bit, set auto refresh interval
; |||||||___________ RFINT1 bit, (RFINT5-0)
; ||||||____________ RFINT2 bit
; |||||_____________ RFINT3 bit
; ||||______________ RFINT4 bit
; |||_______________ RFINT5 bit
; ||________________ RRLD bit, counter refresh strat control
; |_________________ SELF bit, self refresh control
;
;
; This register sets various SDRAM refresh controls. When SDRAM control is not set for
; any area, the setting of this register is meaningless, but do not change the register
; value at initial state. When a read is performed using a read-modify-write
; instruction, 0 always returns from the SELF, RRLD, and PON bits.
;
; Bit description:
;
;
; TRC2 TRC1 TRC0 : Refresh Cycle
; 0 0 0 : 4
; 0 0 1 : 5
; 0 1 0 : 6
; 0 1 1 : 7
; 1 0 0 : 8
; 1 0 1 : 9
; 1 1 0 : 10
; 1 1 1 : 11
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -