config1cfg_c.c

关于硬件系统设计不可多得的参考程序

/*   Do *not* directly modify this file.  It was    */
/*   generated by the Configuration Tool; any  */
/*   changes risk being overwritten.                */

/* INPUT config1.cdb */

/*  Include Header File  */
#include "config1cfg.h"

/*  Config Structures */
EMIF_Config emifCfg0 = {
    0x0020,        /*  Global Control Register   */
    0x0000,        /*  Global Reset Register   */
    0x2fff,        /*  CE0 Space Control Register 1   */
    0x5fff,        /*  CE0 Space Control Register 2   */
    0x5fff,        /*  CE0 Space Control Register 3   */
    0x2fff,        /*  CE1 Space Control Register 1   */
    0x5fff,        /*  CE1 Space Control Register 2   */
    0x5fff,        /*  CE1 Space Control Register 3   */
    0x2fff,        /*  CE2 Space Control Register 1   */
    0x5fff,        /*  CE2 Space Control Register 2   */
    0x5fff,        /*  CE2 Space Control Register 3   */
    0x2fff,        /*  CE3 Space Control Register 1   */
    0x5fff,        /*  CE3 Space Control Register 2   */
    0x5fff,        /*  CE3 Space Control Register 3   */
    0xf948,        /*  SDRAM Control Register 1   */
    0x0080,        /*  SDRAM Period Register   */
    0x0000,        /*  SDRAM Initialization Register   */
    0x03ff         /*  SDRAM Control Register 2   */
};

MCBSP_Config mcbspCfg0 = {
    0x0000,        /*  Serial Port Control Register 1   */
    0x0000,        /*  Serial Port Control Register 2   */
    0x0000,        /*  Receive Control Register 1   */
    0x0000,        /*  Receive Control Register 2   */
    0x0000,        /*  Transmit Control Register 1   */
    0x0000,        /*  Transmit Control Register 2   */
    0x0000,        /*  Sample Rate Generator Register 1   */
    0x0000,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x0000,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */
    0x0000,        /*  Receive Channel Enable Register Partition D   */
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */
    0x0000,        /*  Transmit Channel Enable Register Partition D   */
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */
    0x0000,        /*  Transmit Channel Enable Register Partition G   */
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

PLL_Config pllCfg0 = {
    0x0000,        /*  PLL Response After Idle (IAI)   */
    0x0000,        /*  Response to Loss of PLL Core Lock (IOB)   */
    0x0009,        /*  PLL Multiply Value (PLL_MULT)   */
    0x0003         /*  PLL Divide Value (PLL_DIV)   */
};

TIMER_Config timerCfg0 = {
    0x0010,        /*  Timer Control Register (TCR)   */
    0x0000,        /*  Timer Period Register (PRD)   */
    0x0000         /*  Timer Prescalar Register (PRSC)   */
};

/*  Handles  */

/*
 *  ======== CSL_cfgInit() ========  
 */
void CSL_cfgInit()
{
    PLL_config(&pllCfg0);
}